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Conference Presentation, Fireside Chat, Panel

AI for Chip Design & Chip Design for AI | Ricursive Intelligence | RAISE Summit 2026

  • The company plans a three-phase evolution from accelerating current layout optimization to full end-to-end chip design, aiming to reduce design timelines from over a year to significantly shorter durations and eliminate reliance on hundreds or thousands of human experts using outdated tools.
  • A dual-loop optimization strategy involving an outer language model and an inner loop running 100 to 1,000 times faster than traditional methods is predicted to enable better chip performance, with architectural customization potentially yielding 20x or greater gains compared to the approximate 20% improvements achievable through downstream physical design.
  • Future phases intend to allow frontier labs to break hardware constraints by co-evolving models and chips in a recursive self-improving loop, while simultaneously establishing a platform for application companies to achieve workload-specific customization that could result in multiplier performance gains from even minor percentage optimizations.
  • The company expects a significant increase in custom chip deployment across robotics, automotive, self-driving, AR, VR, and space exploration sectors, supported by AI capabilities that translate high-level code like PyTorch down to machine code (PTX) and simplify programming stacks for specialized model serving.
  • Current technology deployment has already occurred across five generations of Google TPUs, Google Pixel, Waymo, Axion CPU chips, and scaled adoption by external partners like MediaTek, with future plans to apply new AI methods to accelerate physical design and verification from weeks or months down to hours.
  • The long-term mission focuses on achieving the frontier of cost, capability, and efficiency through recursive self-improvement where AI designs its own chips and those chips develop subsequent AI generations, encompassing a spectrum of architectures from general-purpose CPUs and GPUs to specialized etch and Talus designs.