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Conference Presentation, Product Demonstration

AI That Designs Its Own Chips: Ricursive's Anna Goldie and Azalia Mirhoseini

Company Formation and Core Thesis

  • Anna and Azalea founded Recursive Intelligence to apply AI to chip design, establishing a recursive loop where AI optimizes the physical hardware substrate that runs AI.
  • The founders have a combined 10-year history collaborating across Google Brain, Anthropic, and DeepMind, with backgrounds including Stanford faculty and PhD research.
  • Their foundational technology, AlphaChip, was published in Nature and successfully integrated into the tape-out of four generations of Google's TPU data center chips.
  • AlphaChip layouts have also been adopted in Google's Axion CPUs, Pixel phones, and autonomous vehicle chips, alongside external adoption by MediaTek.
  • The company's mission is to accelerate, democratize, and eventually vertically integrate into the chip design workflow to address the high stakes of modern semiconductor development.

Phase 1: Acceleration and Efficiency

  • Recursive Intelligence is currently focused on compressing the two longest poles of chip design: physical design (placing billions of transistors) and design verification (logic correctness).
  • These traditional processes typically consume up to one year and require hundreds or thousands of human experts.
  • The economic pressure is extreme; a single day of delay for a chip like NVIDIA's Blackwell represents an opportunity cost of approximately $225 million.
  • The company aims to help existing chipmakers reduce time-to-market, lower costs, and improve the environmental footprint of chip production.
  • To achieve this, Recursive is redesigning tools to be 100,000x faster in raw computation, enabling AI and reinforcement learning loops to iterate exponentially faster.

Technical Implementation and Performance

  • Recursive has built a static timing analysis (STA) engine that matches commercial tools in fidelity while operating 1,000x faster, providing immediate feedback signals for AI optimization.
  • AI agents utilizing these accelerated tools have generated chip placements characterized by organic, curved shapes rather than the regular, aligned patterns typical of human experts.
  • These AI-generated layouts are designed to minimize wire lengths, resulting in measurable performance improvements over traditional designs.
  • The company employs a hybrid team combining LLM experts (from projects like CoD, Gemini, and Grok) with chip design specialists to drive cross-stack optimization.

Phase 2: Democratization and the Platform Model

  • The second phase aims to create a "designless" platform where companies provide a workload (e.g., a future LLM) and Recursive delivers a GDS2 clean layout ready for fabrication.
  • This model intends to unlock custom chip design for any company with sufficient workload scale, removing the need for internal teams of hundreds of engineers.
  • The goal is to enable a "Cambrian explosion" of varied, highly customized chips optimized for specific use cases, including frontier models, low-power devices, and high-throughput systems.
  • This approach mirrors the "Fabless" revolution, where companies like NVIDIA and Apple focus on architecture while TSMC handles fabrication; Recursive aims to handle the entire design automation layer.

Phase 3: Vertical Integration and Future Outlook

  • Phase three envisions vertical integration where Recursive designs, builds, trains models, and serves intelligence using its own co-evolved hardware.
  • The founders anticipate that this self-reinforcing loop will allow them to match or surpass capabilities achievable by others at a price point currently impossible to reach.
  • The economic model relies on the principle that even a 1% performance improvement for a chip serving a frontier AI model represents a massive financial gain, justifying the cost of specialized design.
  • Recursive introduces "compute" as a new variable or "knob" to trade off design runtimes against performance gains, scaling automation to enable thousands of unique chip variations.