June Paik (FuriosaAI): Tensor Contraction Processor: NextGen AI Inference Chip for Data Centers

Company Overview & Strategic Focus

• Jun Paek, CEO and co-founder of Furiosa AI (Seoul-based startup, 8-year history), introduced the firm's focus on natively designed silicon chips for data center inference.
• The company identifies a paradigm shift from model training to inference-time compute, driven by frontier agentic models (e.g., GPT, DeepSea) requiring high-scale reasoning, planning, and automation.
• Furiosa AI is launching "Renegade," their second-generation chip, to address infrastructure readiness, energy constraints, and the need for economic sustainability in AI.

Market Context & Energy Constraints

• Forecasting suggests a need to construct thousands of gigawatt-scale data centers within the next five years to meet massive AI infrastructure demand.
• Current energy capacity is a bottleneck; Korea's peak national energy consumption recently reached nearly 93 gigawatts, illustrating the difficulty of scaling power generation in short timeframes.
• The current market is characterized by massive CAPEX investments and sovereign AI initiatives, yet many AI companies face unsustainable business models due to high infrastructure costs.

Renegade Chip Specifications & Performance

• Compute Power: Delivers 512 teraflops of floating-point 8-bit performance and approximately 1 petaflop of integer 4-bit performance.
• Memory Architecture: Features a high compute-to-memory ratio with a memory bandwidth of 1.5 terabytes per second, addressing a key determinant of LLM end-to-end performance.
• Power Efficiency: Consumes 180 watts, compared to over 300 watts for equivalent performance GPUs, translating to an estimated $20 savings per year per watt and $10 billion in savings over five years for a 100-megawatt data center.
• Manufacturing: Built using TSMC's 5-nanometer node, integrating 40 billion transistors, and utilizing advanced memory from SK Hynix.
• Benchmarks: Outperforms the NVIDIA H100 by 190% on the "tokens per second per watt" metric under real-world usage scenarios.

Architectural Innovation: Tensor Contraction Processor (TCP)

• The architecture is designed as a "Tensor Contraction Processor" to achieve a balance of high performance, energy efficiency, and flexibility.
• Abstraction Shift: Treats "tensor contraction" (generalized multi-dimensional matrix multiplication) as a fundamental hardware primitive, contrasting with the fixed 2D matrix multiplication primitives used in current hardware.
• Design Philosophy: Employs a holistic co-design approach integrating algorithm, software, and hardware to accommodate future innovations like Mixture of Experts (MoE), continuous batching, in-flight batching, page attention, and quantization.
• Flexibility Goal: Ensures the hardware remains adaptable to software optimizations, avoiding the efficiency degradation seen when rigid hardware architectures cannot reflect the latest algorithmic advances.

Commercial Status & Strategic Vision

• Deployment: The Renegade chip is currently in the sampling phase with enterprise clients globally.
• Target Sectors: Applications are active or targeting manufacturing, life sciences, energy, and public sector sovereign AI initiatives.
• Value Proposition: Furiosa AI urges enterprises to control and own their full AI stack, including the computing layer, to manage costs and avoid dependency on external solutions.
• Future Outlook: The company aims to lead the AI computing space through continued innovation, viewing the transition to efficient AI hardware as comparable to the shift from gasoline to electric vehicles in transportation.