Lecture, Other
Matt Godbolt: Advanced Skylake Deep Dive
- Matt Godbolt plans to resume work at HRT next week after his non-compete agreement concludes.
- Branch prediction topics will be addressed after the main presentation or in informal settings due to an anticipated five-minute time constraint for the CPU pipeline back end.
- Presentation content will compare Skylake architecture to modern server CPUs, utilizing C++ example code after an OCaml attempt failed to generate equivalent assembly.
- The x86 pre-decoder may conservatively tag simple instructions as complex, potentially causing three-cycle stalls when length-changing prefixes are used.
- Skylake's loop stream detector is expected to be disabled due to an unfixable hardware bug, with potential reduced effectiveness in code containing multiple entry points per 32-byte block.
- Skylake micro-op cache configurations may differ in newer machines, potentially supporting six ways within 64 bytes compared to current specifications.
- Renaming on newer architectures like Alder Lake may employ move elimination to handle small increments without issuing micro-operations, while shift operations taking two cycles may result from a hidden add.
- Integer divide operations on Skylake are significantly slower, estimated at roughly 100 cycles for 64-bit versions, representing a worst-case scenario compared to the four-micro-op limit of the first decoder.
- The store buffer is expected to hold store operations until retirement, delaying transfer to real memory, while retirement generally allows up to four micro-operations per cycle.
- Floating-point denormal numbers may trigger a pipeline flush and a return to the microcode sequencer to handle exceptions.
- Slides containing references and data will be released post-presentation, alongside speculation that Intel limits public architectural documentation to protect legacy compatibility and intellectual property.
- Intel may provide detailed "pink books" or "yellow books" to high-volume chip customers, while branch prediction behavior varies significantly between Intel and AMD, with Skylake potentially featuring a specific bit 5 vulnerability in its branch predictor.