Jul 22, 2026, 9:22 AM ETFireside Chat, Panel, Conference Presentation

The Chip Revolution: Beyond GPUs to Tomorrow's Processors | RAISE Summit 2026

Inference accelerator spending is projected to overtake training spend by next year, potentially weakening NVIDIA's current market lock-in.
The shift from chat-based applications to autonomous agents is increasing workload durations and tilting compute requirements toward CPU capabilities.
System-level bottlenecks are evolving from raw compute power to memory bandwidth, energy efficiency, and thermal management.
Hardware design units are expanding from single chips to entire racks or clusters, as large mixture-of-expert models require thousands of chips to operate concurrently.
Unconventional.ai is betting on "dynamics" (physics-based computation via differential equations) rather than traditional digital or purely analog methods, aiming for 1,000x energy efficiency over von Neumann architectures.
Etched is vertically integrating entire inference clusters (custom chips, boards, networking, cooling) to serve trillion-parameter models, with first chips shipping in the summer.
Fractile focuses on system-level speed to enable autonomous agents to generate hundreds of millions of tokens, treating time as the primary bottleneck rather than just throughput.

GPU systems currently operate at 30-40% Matrix Multiply Utilization (MFU) due to thermal throttling, leaving over $0.50 in potential value per dollar unserved.
Memory bandwidth is the critical lever for balancing speed and utilization; increasing bandwidth allows for smaller batch sizes without sacrificing throughput efficiency.
Etched's architecture addresses thermal limits by introducing new power technologies to prevent chips from self-regulating at lower clock speeds.
Fractile notes that while current models are memory-bound, future software architectures (e.g., smaller, iterative models) may shift the bottleneck back to compute.
Co-locating memory and compute within a single unit, as proposed by Unconventional.ai, is intended to eliminate data movement overheads and reduce energy consumption.
Data center consolidation is expected to continue as the economic viability of advanced nodes (e.g., 2nm) requires $40 billion fab investments, favoring large-scale cluster deployment over edge inference.
Edge deployment for frontier models is deemed unlikely until "capability saturation" is reached, as data center solutions remain more energy- and cost-efficient per query due to throughput amortization.

Software porting barriers are being lowered as AI models demonstrate capabilities in writing optimized kernels, potentially making manual kernel engineering obsolete within 1-2 years.
Fractile has built a proprietary software layer enabling agents to recursively improve performance via profiling traces, addressing the "observer effect" where profiling alters chip performance.
Unconventional.ai plans to tape out a new design every four months to maintain agility, treating hardware iteration velocity as a competitive advantage.
Etched employs a "pre-fetching" strategy, building racks, cooling systems, and software stacks before the silicon arrives to ensure production is the final step.
Supply chain ramping is identified as a critical path, requiring vendors to secure gigawatt-scale manufacturing capacity years before product success is realized.
Etched views hyperscaler in-house chip programs (e.g., Google TPU, AWS Trainium) as non-existential threats, noting these teams often lag the technological frontier to serve primary revenue drivers like search or cloud services.
Large corporations are viewed as hesitant to take "big swings" in architecture; Unconventional.ai leverages this by pursuing high-risk, high-reward unconventional computing paradigms that large teams cannot easily scale.

Lightspeed is a partner and investor in Unconventional.ai, though the speaker does not sit on its board.
The panel represents three distinct architectural bets: Unconventional.ai (physics/dynamics), Etched (integrated cluster infrastructure), and Fractile (high-speed system architecture).