New patent application published for: DISPLAY CHIP AND MANUFACTURING METHOD

DISPLAY CHIP AND MANUFACTURING METHOD

Claims

1. A display chip, comprising: a chip structure, comprising a first semiconductor layer, a quantum well light emitting layer, and a second semiconductor layer that are arranged in sequence, wherein one of the first semiconductor layer and the second semiconductor layer is an n-type semiconductor layer, and the other one is a p-type semiconductor layer; wherein the first semiconductor layer, the quantum well light emitting layer, and the second semiconductor layer are all nitrogen-polarity film layers.
2. The display chip of claim 1, wherein the chip structure further comprises a fourth undoped semiconductor layer, a first barrier layer, a first superlattice layer, and a second superlattice layer that are arranged in sequence between the first semiconductor layer and the quantum well light emitting layer; and the fourth undoped semiconductor layer, the first barrier layer, the first superlattice layer, and the second superlattice layer are all nitrogen-polarity film layers.
3. The display chip of claim 1, wherein the first semiconductor layer comprises a heavily doped semiconductor layer and a lightly doped semiconductor layer located between the heavily doped semiconductor layer and the quantum well light emitting layer; and the heavily doped semiconductor layer and the lightly doped semiconductor layer are both nitrogen-polarity film layers.
4. The display chip of claim 1, wherein the quantum well light emitting layer comprises a fifth undoped semiconductor layer, a first well layer, a first cap layer, a second barrier layer, a sixth undoped semiconductor layer, a second well layer, a second cap layer, and a third barrier layer that are arranged in sequence between the first semiconductor layer and the second semiconductor layer; and the fifth undoped semiconductor layer, the first well layer, the first cap layer, the second barrier layer, the sixth undoped semiconductor layer, the second well layer, the second cap layer, and the third barrier layer are all nitrogen-polarity film layers.
5. The display chip of claim 1, wherein the second semiconductor layer comprises an electron blocking layer, a hole injection layer, and an ohmic contact layer that are arranged in sequence on a side of the quantum well light emitting layer away from the first semiconductor layer; and the electron blocking layer, the hole injection layer, and the ohmic contact layer are all nitrogen-polarity film layers.
6. The display chip of claim 1, wherein the chip structure further comprises a first transparent conductive layer, a first reflective layer, and a bonding layer that are sequentially located on a side of the second semiconductor layer away from the quantum well light emitting layer.
7. The display chip of claim 1, wherein the chip structure further comprises a protective layer located between the quantum well light emitting layer and the second semiconductor layer.
8. The display chip of claim 1, wherein the display chip further comprises a base plate; and the base plate is bonded to a side of the chip structure away from the first semiconductor layer.
9. The display chip of claim 8, wherein the display chip further comprises a passivation layer and a second reflective layer; and the passivation layer is located on a side of the chip structure away from the base plate and covers a side wall of the chip structure, and the second reflective layer covers the passivation layer.
10. The display chip of claim 9, wherein the display chip further comprises a second transparent conductive layer located on a side of the second reflective layer away from the base plate, and the second transparent conductive layer penetrates through the second reflective layer and the passivation layer and is connected to the first semiconductor layer.
11. The display chip of claim 10, wherein the display chip further comprises a third reflective layer located on a peripheral side of the chip structure, and a microlens located on a side of the second transparent conductive layer away from the chip structure.
12. The display chip of claim 1, wherein the quantum well light emitting layer comprises a red light quantum well light emitting layer.
13. A manufacturing method of a display chip, comprising: forming a base; forming a chip structure on one side of the base, the chip structure comprising a first semiconductor layer, a quantum well light emitting layer, and a second semiconductor layer that are arranged in sequence on the one side of the base, wherein one of the first semiconductor layer and the second semiconductor layer is an n-type semiconductor layer, and the other one is a p-type semiconductor layer, wherein the first semiconductor layer, the quantum well light emitting layer, and the second semiconductor layer are all nitrogen-polarity film layers; and removing the base.
14. The manufacturing method of a display chip of claim 13, wherein the base comprises a substrate, a buffer layer, and an undoped semiconductor composite layer; the forming the base comprises: providing the substrate; forming the buffer layer on one side of the substrate; and forming the undoped semiconductor composite layer on a side of the buffer layer away from the substrate, the chip structure being located on a side of the undoped semiconductor composite layer away from the buffer layer; and wherein the buffer layer and the undoped semiconductor composite layer are both nitrogen-polarity film layers.
15. The manufacturing method of a display chip of claim 14, wherein the undoped semiconductor composite layer comprises a plurality of undoped semiconductor layers and at least one insertion layer that are arranged in a stacked manner, and there is one insertion layer between any two adjacent undoped semiconductor layers; and the undoped semiconductor layers and the insertion layer are all nitrogen-polarity film layers.
16. The manufacturing method of a display chip of claim 15, wherein the plurality of undoped semiconductor layers comprise a first undoped semiconductor layer, a second undoped semiconductor layer, and a third undoped semiconductor layer, and the at least one insertion layer comprises a first insertion layer and a second insertion layer; the first undoped semiconductor layer, the first insertion layer, the second undoped semiconductor layer, the second insertion layer, and the third undoped semiconductor layer are arranged in sequence between the buffer layer and the first semiconductor layer; and the first undoped semiconductor layer, the second undoped semiconductor layer, and the third undoped semiconductor layer each comprise a u-GaN layer, the first insertion layer comprises a porous SiNx layer, and the second insertion layer comprises an AIN layer.
17. The manufacturing method of a display chip of claim 14, wherein the removing the base comprises: removing the substrate; and removing the buffer layer and the undoped semiconductor composite layer.
18. The manufacturing method of a display chip of claim 13, wherein before the removing the base, the method further comprises: bonding a side of the chip structure away from the base to a base plate.
19. The manufacturing method of a display chip of claim 18, wherein after the removing the base, the method further comprises: forming a passivation layer on a side of the chip structure away from the base plate, and the passivation layer covers a side wall of the chip structure; and forming a second reflective layer on a surface of the passivation layer.
20. The manufacturing method of a display chip of claim 19, wherein the method further comprises: forming a second transparent conductive layer on a side of the second reflective layer away from the base plate, and the second transparent conductive layer penetrates through the second reflective layer and the passivation layer and is connected to the first semiconductor layer; and forming a microlens on a side of the second transparent conductive layer away from the base plate.