New patent application published for: DISPLAY PANEL, DRIVING METHOD THEREOF AND DISPLAY DEVICE

DISPLAY PANEL, DRIVING METHOD THEREOF AND DISPLAY DEVICE

Claims

1. A display panel, comprising a plurality of subpixels and a shift register circuit, wherein the shift register circuit comprises a plurality of cascaded shift register units electrically connected to the plurality of subpixels, wherein at least one of the plurality of shift register units comprises: an input module, wherein the input module, in response to a signal output by a clock signal terminal, is electrically connected to a first input terminal and a first node, and is electrically connected to a second input terminal and a second node; a first inverter and a second inverter, wherein an input terminal of the first inverter is electrically connected to the first node, and an output terminal of the first inverter is electrically connected to the second node; and an input terminal of the second inverter is electrically connected to the second node, and an output terminal of the second inverter is electrically connected to the first node; a first cascade output module electrically connected to a first fixed potential signal terminal and a first cascade output terminal in response to a signal of the first node; and a second cascade output module electrically connected to a second fixed potential signal terminal and a second cascade output terminal in response to a signal of the second node, wherein an output terminal of the at least one shift register unit is electrically connected to the first node.
2. The display panel according to claim 1, wherein a signal input to the first fixed potential signal terminal has a same type as a signal of the second fixed potential signal terminal.
3. The display panel according to claim 1, wherein the first fixed potential signal terminal is electrically connected to the second fixed potential signal terminal.
4. The display panel according to claim 1, wherein signals input to the first input terminal and the second input terminal are inverse to each other.
5. The display panel according to claim 1, wherein a signal output by the clock signal terminal comprises a plurality of active pulses; a rising edge of a signal input to the first input terminal and a falling edge of a signal input to the second input terminal are both located between two adjacent ones of the plurality of active pulses of the signal output by the clock signal terminal; and a falling edge of the signal input to the first input terminal and a rising edge of the signal input to the second input terminal are both located between another two adjacent ones of the plurality of active pulses of the signal output by the clock signal terminal.
6. The display panel according to claim 1, wherein the clock signal terminal comprises a first clock signal terminal and a second clock signal terminal; in two adjacent stages of shift register units, the input module of a one-stage shift register unit is responsive to a signal output by the first clock signal terminal, and the input module of—another stage shift register unit is responsive to a signal output by the second clock signal terminal; and in two adjacent stages of shift register units, the second cascade output terminal of a previous-stage shift register unit is electrically connected to the first input terminal of a next-stage shift register unit, and the first cascade output terminal of the previous-stage shift register unit is electrically connected to the second input terminal of the next-stage shift register unit.
7. The display panel according to claim 6, wherein the signal output by the second clock signal terminal is a disable level in response to the signal output by the first clock signal terminal being an enable level; and the signal output by the first clock signal terminal is a disable level in response to the signal output by the second clock signal terminal being the enable level.
8. The display panel according to claim 1, wherein the input module comprises a first input transistor and a second input transistor, wherein a first electrode of the first input transistor is electrically connected to the first input terminal, and a second electrode of the first input transistor is electrically connected to the first node; a first electrode of the second input transistor is electrically connected to the second input terminal, and a second electrode of the second input transistor is electrically connected to the second node; a gate of the first input transistor and a gate of the second input transistor are electrically connected to the clock signal terminal; and the first input transistor and the second input transistor have a same channel type.
9. The display panel according to claim 1, wherein the first cascade output module comprises a first output transistor, and the second cascade output module comprises a second output transistor, wherein a first electrode of the first output transistor is electrically connected to the first fixed potential signal terminal, a second electrode of the first output transistor is electrically connected to the first cascade output terminal, and a gate of the first output transistor is electrically connected to the first node; a first electrode of the second output transistor is electrically connected to the second fixed potential signal terminal, a second electrode of the second output transistor is electrically connected to the second cascade output terminal, and a gate of the second output transistor is electrically connected to the second node; and the first output transistor and the second output transistor have a same channel type.
10. The display panel according to claim 9, wherein the first output transistor and the second output transistor are both P-type transistors.
11. The display panel according to claim 1, wherein a signal output by the first cascade output terminal and a signal output by the second cascade output terminal have opposite phases.
12. The display panel according to claim 1, wherein the first inverter comprises a first transistor and a second transistor having different channel types, wherein a first electrode of the first transistor is electrically connected to a first potential signal terminal, a second electrode of the first transistor is electrically connected to the second node, and a gate of the first transistor is electrically connected to the first node; and a first electrode of the second transistor is electrically connected to a second potential signal terminal, a second electrode of the second transistor is electrically connected to the second node, and a gate of the second transistor is electrically connected to the first node; and the second inverter comprises a third transistor and a fourth transistor having different channel types, wherein a first electrode of the third transistor is electrically connected to the first potential signal terminal, a second electrode of the third transistor is electrically connected to the first node, and a gate of the third transistor is electrically connected to the second node; and a first electrode of the fourth transistor is electrically connected to the second potential signal terminal, a second electrode of the fourth transistor is electrically connected to the first node, and a gate of the fourth transistor is electrically connected to the second node.
13. The display panel according to claim 1, wherein the at least one shift register unit further comprises a third inverter, wherein an input terminal of the third inverter is electrically connected to the second node, and an output terminal of the third inverter is electrically connected to the output terminal of the at least one shift register unit.
14. The display panel according to claim 1, wherein the shift register circuit further comprises a starting signal line and a fourth inverter, wherein in a first-stage shift register unit, one of the first input terminal and the second input terminal is electrically connected to the starting signal line and an input terminal of the fourth inverter, and another of the first input terminal and the second input terminal is electrically connected to an output terminal of the fourth inverter.
15. The display panel according to claim 1, wherein at least one of the plurality of subpixels comprises a pixel driving circuit, the pixel driving circuit comprises a light-emitting control module, and the shift register circuit is electrically connected to the light-emitting control module.
16. A display device, comprising a display panel, wherein the display panel comprises a plurality of subpixels and a shift register circuit, and the shift register circuit comprises a plurality of cascaded shift register units electrically connected to the plurality of subpixels, wherein at least one of the plurality of shift register units comprises: an input module, wherein the input module, in response to a signal output by a clock signal terminal, is electrically connected to a first input terminal and a first node, and is electrically connected to a second input terminal and a second node; a first inverter and a second inverter, wherein an input terminal of the first inverter is electrically connected to the first node, and an output terminal of the first inverter is electrically connected to the second node; and an input terminal of the second inverter is electrically connected to the second node, and an output terminal of the second inverter is electrically connected to the first node; a first cascade output module electrically connected to a first fixed potential signal terminal and a first cascade output terminal in response to a signal of the first node; and a second cascade output module electrically connected to a second fixed potential signal terminal and a second cascade output terminal in response to a signal of the second node, wherein an output terminal of the at least one shift register unit is electrically connected to the first node.
17. The display device according to claim 16, wherein a signal input to the first fixed potential signal terminal has a same type as a signal of the second fixed potential signal terminal.
18. The display device according to claim 16, wherein the first fixed potential signal terminal is electrically connected to the second fixed potential signal terminal.
19. The display device according to claim 16, wherein signals input to the first input terminal and the second input terminal are inverse to each other.
20. A driving method of a display panel, wherein the display panel comprises a shift register circuit, and the shift register circuit comprises a plurality of cascaded shift register units, wherein at least one of the plurality of shift register units comprises: an input module, wherein the input module is electrically connected to a first input terminal and a first node in response to a signal output by a clock signal terminal, and is electrically connected to a second input terminal and a second node in response to the signal output by the clock signal terminal; a first inverter and a second inverter, wherein an input terminal of the first inverter is electrically connected to the first node, and an output terminal of the first inverter is electrically connected to the second node; and an input terminal of the second inverter is electrically connected to the second node, and an output terminal of the second inverter is electrically connected to the first node; a first cascade output module electrically connected to a first fixed potential signal terminal and a first cascade output terminal in response to a signal of the first node; and a second cascade output module electrically connected to a second fixed potential signal terminal and a second cascade output terminal in response to a signal of the second node, wherein an output terminal of the at least one shift register unit is electrically connected to the first node; wherein an operating cycle of the at least one shift register unit comprises a first phase and a second phase, and the driving method comprises: in the first phase, providing, by the input module, an enable level to the first node and a disable level to the second node in response to the signal output by the clock signal terminal, wherein the enable level is configured to control the first cascade output module to be turned on, and the disable level is configured to control the second cascade output module to be turned off; providing, by the first cascade output module, the disable level to the first cascade output terminal in response to the signal of the first node; and providing, by the second cascade output module, the enable level to the second cascade output terminal in response to the signal of the second node; and in the second phase, providing, by the input module, the disable level to the first node and the enable level to the second node in response to the signal output by the clock signal terminal; providing, by the first cascade output module, the enable level to the first cascade output terminal in response to the signal of the first node; and providing, by the second cascade output module, the disable level to the second cascade output terminal in response to the signal of the second node.