New patent application published for: TRANSMISSION AND RECEPTION SYSTEM AND SEMICONDUCTOR APPARATUS USING THE TRANSMISSION AND RECEPTION SYSTEM

TRANSMISSION AND RECEPTION SYSTEM AND SEMICONDUCTOR APPARATUS USING THE TRANSMISSION AND RECEPTION SYSTEM

Claims

1. A semiconductor apparatus comprising: a first semiconductor chip including a transmission circuit, the transmission circuit configured to output a transmission signal based on an input signal; a signal transmission line to transmit the transmission signal; and a second semiconductor chip including a reception circuit, the reception circuit configured to shift a voltage level of the transmission signal to generate an output signal, wherein the transmission circuit provides a duty cycle offset which is complementary with a duty cycle offset of the reception circuit.
2. The semiconductor apparatus according to claim 1, wherein the transmission circuit provides the duty cycle offset which is complementary with the duty cycle offset of the reception circuit to cancel the duty cycle offsets of the transmission circuit and reception circuit.
3. The semiconductor apparatus according to claim 1, wherein: the transmission circuit operates in a first power domain, and the reception circuit operates in a second power domain different from the first power domain.
4. The semiconductor apparatus according to claim 1, wherein the transmission circuit comprises a plurality of driver circuits having different duty cycle offsets and each configured to drive the input signal, and the transmission circuit is configured to generate the transmission signal from one of output signals of the plurality of driver circuits.
5. The transmission and reception system according to claim 1, wherein the transmission circuit comprises: a repeater circuit configured to generate a first signal by buffering the input signal; a duty adjustment circuit configured to generate a second signal by changing a duty cycle of the input signal; and a transmission selection circuit configured to output one of the first and second signals based on a transmission control signal, wherein the transmission circuit generates the transmission signal from the output signal of the transmission selection circuit.
6. The semiconductor apparatus according to claim 1, wherein the reception circuit comprises a plurality of level shifters having different duty cycle offsets, wherein each of the level shifters is configured to receive the transmission signal to shift a voltage level of the transmission signal, and wherein the reception circuit is configured to generate the output signal based on at least one of output signals of the plurality of level shifters.
7. The transmission and reception system according to claim 1, wherein the reception circuit comprises: a first level shifter configured to generate a first shifted signal by shifting the voltage level of the transmission signal; a second level shifter configured to generate a second shifted signal by shifting the voltage level of the transmission signal; a mixing circuit configured to output a mixed signal by mixing the first and second shifted signals; and a reception selection circuit configured to generate the output signal from one of the mixed signal and the second shifted signal based on a reception control signal.
8. The semiconductor apparatus according to claim 1, wherein the signal transmission line is a chiplet interconnection.
9. A semiconductor apparatus comprising: a base chip including a transmission circuit, the transmission circuit configured to output a transmission signal based on an input signal; a core chip stacked on the base chip, including a reception circuit, the reception circuit configured to shift a voltage level of the transmission signal to generate an output signal an through electrode to transmit the transmission signal from the base chip to the core chip; and wherein the transmission circuit provides a duty cycle offset which is complementary with a duty cycle offset of the reception circuit.
10. The semiconductor apparatus according to claim 9, wherein the transmission circuit provides the duty cycle offset which is complementary with the duty cycle offset of the reception circuit to cancel the duty cycle offsets of the transmission circuit and reception circuit.
11. The semiconductor apparatus according to claim 9, wherein: the transmission circuit operates in a first power domain, and the reception circuit operates in a second power domain different from the first power domain.
12. The semiconductor apparatus according to claim 9, wherein the transmission circuit comprises a plurality of driver circuits having different duty cycle offsets and each configured to drive the input signal, and the transmission circuit is configured to generate the transmission signal from one of output signals of the plurality of driver circuits.
13. The transmission and reception system according to claim 9, wherein the transmission circuit comprises: a repeater circuit configured to generate a first signal by buffering the input signal; a duty adjustment circuit configured to generate a second signal by changing a duty cycle of the input signal; and a transmission selection circuit configured to output one of the first and second signals based on a transmission control signal, wherein the transmission circuit generates the transmission signal from the output signal of the transmission selection circuit.
14. The semiconductor apparatus according to claim 9, wherein the reception circuit comprises a plurality of level shifters having different duty cycle offsets, wherein each of the level shifters is configured to receive the transmission signal to shift a voltage level of the transmission signal, and wherein the reception circuit is configured to generate the output signal based on at least one of output signals of the plurality of level shifters.
15. The transmission and reception system according to claim 9, wherein the reception circuit comprises: a first level shifter configured to generate a first shifted signal by shifting the voltage level of the transmission signal; a second level shifter configured to generate a second shifted signal by shifting the voltage level of the transmission signal; a mixing circuit configured to output a mixed signal by mixing the first and second shifted signals; and a reception selection circuit configured to generate the output signal from one of the mixed signal and the second shifted signal based on a reception control signal.