Fireside Chat with Sid Sheth, Founder & CEO of d-Matrix | RAISE Summit 2026

D-Matrix Company Profile & Milestones

• Founded in 2019 (seven years prior to the discussion) by the speaker, who serves as Founder and CEO.
• The company is a dedicated inference chip manufacturer building custom silicon, co-packaged subsystems, and deployment software.
• D-Matrix announced that its Gen 1 product (SRAM-based Corsair Accelerator) has officially moved from development into mass production in 2024.
• The company secured a partnership with NVIDIA for customer Parasail (an inference cloud provider) to deploy Blackwell GPUs alongside D-Matrix accelerators for heterogeneous, disaggregated compute workloads.

Strategic Thesis: Inference vs. Training

• D-Matrix differentiated its approach by targeting the "agentic era" where inference, not training, is the primary monetization layer.
• The speaker contrasts training (high performance, massive clusters, scaling out) with inference (high efficiency, low latency, scaling in, minimizing cost per token).
• The company argues that GPUs optimized for training throughput are inefficient for inference because they lack the memory hierarchy required for high interactivity.

Architectural Focus: The Throughput vs. Interactivity Trade-off

• D-Matrix positions itself on the "interactivity" (speed/latency) axis of the standard throughput-per-watt chart, whereas most HBM-based GPUs dominate the "throughput" axis.
• The core technology utilizes In-Memory Compute, integrating compute and memory to minimize data movement, thereby reducing latency and energy consumption.
• Initial Gen 1 architecture relies on SRAM to maximize speed for short-context, high-frequency token generation (machine-to-machine communication).

Next-Gen Technology: 3D Stacked DRAM (IMC)

• D-Matrix is addressing SRAM's capacity limitations by developing a 3D In-Memory Compute (IMC) architecture that stacks DRAM directly on top of the compute logic.
• Timeline & Status: The company spent three years developing this architecture, built multiple POCs, and executed the supply chain; the production tape-out is scheduled for 2027.
• The 2027 product roadmap involves a scalable stacking approach starting with one layer of memory, expanding to four layers, and eventually reaching eight layers (comparable to HBM stacking densities but on the compute stack).
• This hybrid approach aims to simultaneously optimize the X-axis (latency/speed) and shift the Y-axis (throughput/capacity) to handle larger models and longer context windows.

Market Outlook: Coexistence and Disaggregation

• The speaker predicts a market where HBM-based GPUs and specialized inference accelerators will coexist rather than one replacing the other.
• Disaggregated Computing: Large models trained on GPUs will be deployed via a hybrid model where heavy compute pre-fills run on GPUs, while memory-intensive decoding runs on SRAM/DRAM-based accelerators.
• Capacity Limits: D-Matrix acknowledges that even with stacked DRAM, the architecture cannot match the massive capacity of HBM; therefore, pure HBM solutions will remain necessary for the largest models and longest context lengths.
• D-Matrix positions its 2027 Stack DRAM product as a potential first-to-market solution for this specific 3D hybrid architecture, aiming to capture the "holy grail" of high throughput with high interactivity.