Conference Presentation, Panel, Interview
Fireside Chat with Sid Sheth, Founder & CEO of d-Matrix | RAISE Summit 2026
- D-Matrix has announced production-ready Gen 1 SRAM-based inference chips and plans to deploy them to market utilizing built subsystems and software.
- The company anticipates the agentic era will drive demand for inference solutions optimized for throughput, energy efficiency (throughput per watt), and low latency measured in milliseconds per token.
- Forecasts indicate cost per token and latency will remain critical optimization metrics for future agentic workloads.
- SRAM-only architectures are expected to face capacity constraints regarding model size and context length, prompting a market shift toward heterogeneous disaggregated compute where pre-fill operations run on GPUs and memory-intensive tasks utilize SRAM accelerators.
- A strategic transition from SRAM-only architecture to a hybrid approach involves stacking custom DRAM directly on compute, commencing with one memory layer in the next-generation product.
- The stacked DRAM architecture is designed to scale from one layer to four layers, with potential for expansion to eight layers over time.
- Stacked DRAM solutions are projected to increase performance throughput while maintaining high levels of interactivity and speed.
- Both HBM-based GPU solutions and custom inference accelerators are expected to coexist in the market, with GPUs retaining a necessary role for handling full training capabilities as models grow larger.
- Customer adoption may vary between heterogeneous workload designs driven by cost or power constraints and DRAM-based solutions for applications not requiring large context lengths.
- D-Matrix intends to tape out a production version of the stacked DRAM product with a target market release in 2027.
- The company aims to be among the first to launch a product utilizing the stacked DRAM approach in 2027, though it acknowledges uncertainty regarding whether other competitors may release similar solutions concurrently.