Pat Gelsinger & Elad Raz: Where Chips Go After the GPU Era | RAISE Summit 2026

Strategic Shift and Market Trends

• Next Silicon originated in supercomputing (HPC) eight years ago, targeting physical simulations, fluid dynamics, and defense, but has pivoted to AI as the dominant sector.
• Foundational HPC and AI share identical mathematical principles, with AI workloads often being mathematically simpler than complex HPC kernels.
• The industry CPU-to-GPU ratio is shifting from extreme GPU dominance (1:16) back toward balance (1:1 to 1:2) due to the increasing need for CPU affinity in agentic multi-model environments.
• Startups are increasingly betting on non-Transformer architectures to avoid the prohibitive capital requirements (approx. $3 billion) associated with developing 10-trillion-parameter models.
• The distinction between training and inference is decaying; the future view is a single, continuously learning workload rather than separate phases, mimicking human learning cycles.
• Future scientific models are expected to evolve from 2D structures to 3D and 4D models to accurately represent physical realities like molecules and material science.

Next Silicon Architecture and Technology

• The Maverick accelerator integrates a custom RISC-V CPU core alongside its data flow accelerator, allowing a single chip to handle both serial code and parallel workloads.
• The architecture is explicitly software-driven and flexible, designed to accommodate evolving MLOps, including sparse attention, multi-head attention, and frequency-space computations (e.g., Mamba models).
• The system supports legacy and modern codebases, including Fortran, C, CUDA, and Triton, ensuring compatibility with the vast existing HPC ecosystem.
• Next Silicon has completed four tape-outs over eight years, with the second generation currently in production at rack-level scales in national laboratories (DOE/DoD).
• The company predicts that LLMs will increasingly generate codebases for physical simulations, necessitating a unified architecture for both AI and scientific computing within a single memory space.
• A major announcement regarding an AI and GenTech flow is scheduled for later this year.

Industry Philosophy and Future Outlook

• Special-purpose ASICs designed for single algorithms (like early floating-point processors) historically fail as workloads evolve; general-purpose, adaptable architectures are required for longevity.
• Scaling challenges arise when creating "islands of compute" for specialized tasks (e.g., pre-fill vs. decode); integrated architectures prevent this fragmentation at scale.
• Future hardware must achieve a 10,000x improvement in efficiency (performance per power) to make AI viable for solving next-generation challenges in chemistry, biology, and material science.
• Chip design cycles (approx. 3 years) necessitate architectures that are agnostic to future models, as predicting specific algorithmic shifts three years out is impossible.
• The industry is in the "first inning" of AI adoption, with significant demand growth expected beyond current software developer-focused use cases (e.g., GitHub Copilot, Gemini).
• Critical future metrics will focus heavily on performance per watt, with data center power requirements currently underestimated by three to five orders of magnitude.
• Long-term predictions include the integration of cryogenic computing and fundamentally different interconnect architectures to support the next decade of human innovation.