Conference Presentation, Fireside Chat
Pat Gelsinger & Elad Raz: Where Chips Go After the GPU Era | RAISE Summit 2026
- Next Silicon, founded eight years ago, plans to announce a significant update regarding its AI and GenTech flow later this year, leveraging its existing foundation in high-performance computing (HPC) to address AI acceleration for big thinking, agentic, and open-source models such as GLM, Kimmy, and Quan.
- The company anticipates a shift away from specialized ASICs for single tasks toward flexible, software-driven architectures capable of evolving with workloads, expecting that startups inventing new models will likely bet on non-transformer architectures due to the prohibitive $3 billion capital required to train transformer-based models at 10 trillion parameters.
- Next Silicon expects to see a transition in computing infrastructure from single-function chips to rack-level and multi-rack scaling, noting that early customers have tested the technology at scale and that the current 1-to-16 or 1-to-8 CPU-to-GPU market ratios are drifting toward 1-to-2 or 1-to-1 balances.
- The speaker projects that the industry requires a fundamental shift in energy efficiency and computing architecture to enable AI to become 10,000 times better than today for applications in chemistry, biology, bioengineering, and material science.
- Intel forecasts that the boundary between training and inferencing will decay over time, leading to algorithms that enable continuous self-training where workloads dynamically adjust, and anticipates that the "decoding" and "pre-fill" phases of inference will become increasingly similar to training.
- Future computer architectures are expected to evolve from 2D to 3D and 4D representations to accommodate the physical world, molecules, and physical AI, with cryogenic computing predicted to emerge within the coming decade.
- The industry is currently estimated to be in the first inning of AI adoption, yet the speaker notes that current infrastructure is missing three orders of magnitude (10,000x) in performance per power needed for full AI adoption.
- Significant capital expenditures of approximately $150 million are required for every chip generation, implying that only companies that are "very different" can succeed at the top of the market.
- Next Silicon's architecture integrates a RISC-V CPU to handle serial code alongside data flow acceleration for parallel sections, allowing legacy Fortran code to run on modern supercomputing systems while supporting agnostic MLOps environments written in Triton, CUDA, C, or Fortran 77.
- The speaker predicts that the field is changing so rapidly that the AI future two years from now cannot be reliably predicted by anyone, necessitating architectures that can accommodate next-generation algorithmic spaces and unknown models.
- The speaker forecasts that the next 10 years will unleash the greatest period of human scientific endeavor, with the "physical AI moment" expected to change capabilities regarding chat and scientific discovery similar to the impact of the transformer moment.
- Legacy Fortran code used in most supercomputing will continue to require hardware support, and the speaker notes that national laboratories will continue to drive compute innovation and pave the way for the future.
- The speaker anticipates that the "islands of compute" created by specialized architectures are not scalable, and that workloads will continue to evolve, requiring general-purpose hardware to handle whatever kernels or FFTs are thrown at them.
- Next Silicon has spent eight years completing four tape-outs, placing its first generation in all national laboratories, and is currently producing a second generation installed at rack-level scales, with the "Maverick" chip data flow and Arbel RISC-V chip now operational.
- The speaker asserts that AI workloads are simpler than HPC workloads and that HPC and AI share the same mathematical principles, making the transition from HPC to AI a manageable shift for companies with a strong foundation in parallel and serial code acceleration.