Interview, Conference Presentation
The Democratization of Engineering | Sassine Ghazi, Synopsys | RAISE Summit 2026
- The industry is shifting focus from training to inference efficiency as models advance, driving chip design optimization toward performance, energy efficiency, and throughput through general-purpose chips, ASICs, and Customer-Owned Tooling.
- Hardware evolution over the next few years involves increasing heterogeneity using memory, compute, and networking as modular components, while infrastructure requires full-stack silicon customization to address these changes.
- Design margins will be reduced via cross-domain co-design and digital twins, with AI agents currently handling six to eight front-end tasks for code generation and validation to reach an L4 cognitive stage.
- Automation progress in chip design is described as "fantastic" for front-end workflows, though physical implementation still requires manual intervention; earlier five-to-six-year projections for full physical automation were revised downward due to rapid foundation model innovation.
- Advanced silicon capacity constraints regarding logic wafers and memory are driving new design approaches, with expectations that global capacity will be insufficient by 2030 to meet Tesla's envisioned demands for EVs and robotics.
- The market is characterized by a "tale of two" cycles: one driven by AI infrastructure growth and a traditional analog market lifting from lows, while memory cycles historically occurring every three to four years are prolonging due to advanced silicon demand.
- Future priorities include integrating AI into all workflow steps, co-designing across engineering domains to minimize iterations, and reducing costs for robotics, which are currently active but face cost-reduction challenges.
- The outlook remains optimistic regarding demand for advanced silicon to support the physical AI world, acknowledging that while capacity constraints will alter design strategies, they will not eliminate the need for advanced silicon.