Interview, Fireside Chat, Product Demonstration
What will computer chips look like in 2045?
Dwarkesh PatelTom Fox, Chris Oth, Kevin Fisher, Jack Cavalieros, Tyler Osborne, Pushkar Arande, Francesc Campoy, Mark Mandelmann, Shyam Gollakota, Seth Vargoeva
- AI demand is projected to exceed Intel's maximum capacity by 40% to 50%, necessitating a semiconductor supply chain ramp-up that cannot be achieved by Intel alone.
- The 14A process is targeted for production readiness around 2028, requiring finalization of tool sets and process fine-tuning over the next two years to reach volume output of thousands of wafers per week.
- Intel plans to limit innovation in future technology nodes to maintain schedules and will utilize maturity metrics and phase gates to transition technologies from pathfinding to development.
- High-NA EUV adoption is expected to be an optional customer choice for 14A, while EUV remains the primary technology for future nodes, with tool sets for 14A ready from the outset.
- Material strategies include maintaining copper for larger interconnects while transitioning to ruthenium at roughly 20nm pitches and anticipating a future replacement material for the tightest pitches.
- Long-term roadmaps envision 10 to 20 years (by 2045) of stacked transistor and interconnect structures, with thermals identified as a fundamental limiter for 3D devices like CFET.
- Manufacturing strategies involve hybrid bonding to 0.45 micron pitch densities, pursuing both die-to-wafer and wafer-to-wafer approaches, and using "hotboxes" for accelerated experimental prioritization.
- Supply constraints include ASML producing fewer than 100 EUV tools annually without significant increases by decade-end, and an 18-month lead time for new tool orders pushing timelines to 2028.
- Capital expenditure is projected to grow from current levels toward $50 billion to match competitors, with lithography costs doubling every four to five years and current High-NA EUV equipment costing $400 million.
- Market consolidation is expected to continue with only three advanced foundries remaining, while Intel anticipates a slow, scale-focused catch-up to TSMC, targeting 14A density comparable to TSMC's N2 node.
- Operational plans include simplified functional CFET versions in research labs, managing a memory supply crunch larger than the compute crunch, and pursuing additional tool acquisitions to mitigate regional concentration risks.
- Future scenarios include a "pseudo vertical world" where hyperscalers vertically integrate production, the U.S. facing potential revenue losses without increased tool acquisition, and production forecasts remaining flat by 2030 without rapid supply chain growth.