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Cadence and Samsung Foundry Deepen 2nm and 3D‑IC Collaboration to Meet Surging AI Infrastructure and Physical AI Demand

CDNS
  • Cadence & Samsung Foundry announced a multi-year agreement expanding Memory, Interface IP, & agentic AI-optimized GPU-accelerated EDA/SDA flows on Samsung's second-generation 2nm node.
  • The collaboration delivers a signoff-ready platform for next-generation AI infrastructure & physical AI designs across data center, edge, & intelligent devices.
  • The expanded portfolio includes NVIDIA NVLink-C2C-enabled interconnects & CUDA-X GPU-accelerated libraries spanning high-speed SerDes, PCIe, UCIe, & leading memory interfaces on 2nm.
  • Certified design flows include Cadence Innovus for digital implementation, Virtuoso Studio for analog/custom design, Integrity 3D-IC Platform, Voltus IC Power Integrity, Quantus Extraction, & Tempus Timing Solution.
  • Samsung 3D Cube-H design is enabled via hybrid copper bonding (HCB) technology with full system planning, implementation, & signoff flows for tighter connectivity & trusted verification.
  • NVIDIA leverages the platform for high-bandwidth NVLink-C2C interconnects & CUDA-X capabilities to optimize performance & delivery of next-generation AI architectures.
  • Ambarella is developing a next-generation 2nm edge AI platform utilizing Cadence & Samsung IP for PCIe 5.0 to support robotics, drones, autonomous machines, & advanced sensing applications.
  • Cadence & Samsung Foundry will showcase enhanced partnership & design enablement at the Samsung Advanced Foundry Ecosystem (SAFE) 2026 event.