Connecting Chiplets Isn’t Enough - Solving the Data Movement Challenge in Multi-Die Systems - ARTERIS INC

Financial Performance:

• The transcript does not contain specific financial data, revenue figures, profit margins, cash flow statements, or debt metrics as this is a technical webinar rather than a formal earnings call.
• No deferred revenue or industry-specific financial metrics were disclosed.

Guidance and Future Outlook:

• Arteris plans to address multi-vendor chiplet interoperability in the future by leveraging the AMBER C2C standard, though details are reserved for future discussions.
• The company identifies a market trend moving from single-vendor homogenous designs toward an open ecosystem of off-the-shelf chiplets, positioning chiplets as the "new IP."
• Future growth is driven by the increasing adoption of multi-die architectures to support AI workloads and complex computing demands that exceed monolithic silicon limits.

Business Segments and Product Lines:

• Product Lines: Highlights two primary Network-on-Chip (NOC) IP families for multi-die systems:
  • ENCOR: Supports coherent NOC designs for multi-level CPU caches.
  • FlexGen: Supports non-coherent NOC designs, offering "NOC tunneling" to transport native protocols across chiplet boundaries.
• New Capabilities: Introduces "NOC tunneling" to extend NOC logic across chiplet boundaries, preserving Quality of Service (QoS), clock, power, and interrupt signals that standard AXI-to-UCI bridges typically lose.
• Specific Features: FlexGen supports up to eight independent virtual channels for traffic prioritization; ENCOR supports connecting up to four chiplets with up to four UCIe links per chiplet.
• Use Cases: Cites AMD EPYC 9005 and Apple M Ultra as existing examples of successful multi-die implementations using these technologies.

Market and Competitive Landscape:

• Market Drivers: The shift to multi-die is driven by reticle size limits (maximum 858 mm² for monolithic dies), yield improvements on smaller chips, cost efficiency through process node specialization (e.g., leading-edge compute vs. older-node IO), and IP reuse for product portfolios.
• Competition/Standards: Discusses UCIe (Universal Chiplet Interconnect Express) as a standard interface but argues that standard die-to-die protocols are insufficient for single-vendor designs due to protocol translation overhead.
• Architecture Trends: Contrasts "single-vendor" designs (homogenous, internal) with "partner ecosystem" and "open ecosystem" models (heterogenous, external).

Risks and Challenges:

• Interconnect Complexity: Standard AXI-to-UCI bridges often lack bidirectional transaction support, requiring dual PHY channels that increase area and power consumption.
• Data Loss: Converting native NOC protocols to AXI for chiplet transmission results in the loss of out-of-band data (QoS, clock, power control), necessitating complex out-of-band signaling to preserve system behavior.
• Design Partitioning: Poor partitioning decisions can complicate thermal management, traffic flow, and the ability to model the system as a cohesive unit.

Management Commentary and Tone:

• Tone: Confident and authoritative; management asserts that "connectivity alone is not enough" and advocates strongly for NOC tunneling as the superior solution for single-vendor multi-die designs.
• Strategy: Emphasizes the philosophy of designing the interconnect architecture as a monolithic system first, then physically partitioning it into chiplets later, rather than adapting designs to fit chiplet constraints.
• Differentiation: Positions Arteris's NOC tunneling technology as a key differentiator that eliminates protocol translation overhead, minimizes latency, and preserves all system control signals.

Analyst Questions and Answers:

• Q: Request for charts or engineering data. A: The company does not promote chiplets directly but points to external papers on engineering considerations; no specific internal data charts were provided.
• Q: What changes regarding data movement and QoS across a die boundary? A: Ideally, nothing changes if using NOC tunneling; without it, the system behaves like two separate chips, complicating modeling and QoS.
• Q: Why isn't a fast die-to-die link sufficient? A: Speed is insufficient without the transport of non-transactional metadata (QoS, clock, power domains) which is lost when using transaction-only protocols like AXI.
• Q: How do AI workloads drive multi-die adoption? A: AI requires compute density exceeding reticle limits; multi-die allows for economically viable scaling, better yields, and flexible product configurations.

Other Key Points:

• Technical Explanation: A monolithic reticle limit is 26x33mm (858 mm²); multi-die allows scaling beyond this by using silicon interposers for 2.5D integration.
• Process Optimization: Different functions (compute, IO, analog, DRAM) can be fabricated in their optimal process nodes (e.g., 3nm for compute, older nodes for IO) and integrated as separate chiplets.
• Protocol Comparison: The presentation explicitly favors "NOC-to-NOC" tunneling over "AXI-to-UCI" bridging for single-vendor systems to avoid the limitations of unidirectional bridges and data loss.