Your Chip Works. Prove It Is Secure. - ARTERIS INC

Based on the provided transcript, there are no forward-looking financial statements (e.g., revenue guidance, earnings forecasts, capex plans, or market share targets) for Arteris or any other specific company. The content is a technical webinar regarding a security verification tool (PsiQt) and does not contain business strategy, macroeconomic outlooks, or investment guidance.

The only "future-oriented" content regarding timing relates to the adoption of new regulations and the timeline for specific vulnerability releases mentioned by the speakers as context for current urgency:

• Explicit Guidance: None.
• Business-Segment Outlook: None.
• Market and Competitive Outlook: None.
• Macro / Industry Outlook:
  • EU Cyber Resilience Act (CRA) Reporting: The European Union began reporting obligations for all sectors in September 2026; specifications for hardware suppliers entering the EU market are scheduled to be enforced in December 2027 (Speaker: Leon Brown).
  • Hardware Vulnerability Trends: The transcript notes that hardware vulnerabilities discovered in 2026 have already eclipsed the total count from 2025, indicating an accelerating trend in attack discovery speed and volume (Speaker: Leon Brown).
  • Regulatory Compliance Trickle-Down: Future market pressure will see device vendors and semiconductor IP suppliers required to provide security evidence to one another, driven by the EU CRA and U.S. third-party IP (3PIP) requirements (Speaker: Leon Brown).
• Strategic Initiatives:
  • AI-Driven Attack Automation: Management anticipates a future where hardware attack discovery becomes automated at scale using AI tools, which can synthesize decades of research into new exploits in under four minutes, necessitating a shift from functional testing to continuous asset tracking (Speaker: Leon Brown).
  • Tool Integration: Customers are expected to increasingly utilize information flow tracking (PsiQt) to provide sign-off evidence for regulatory compliance (automotive ISO/SAE 21434, EU CRA, U.S. Defense) prior to tape-out, moving beyond standard functional verification (Speaker: Leon Brown & Q&A).
• Risks and Headwinds to Outlook:
  • Pre-Silicon Blind Spots: A significant risk is that functional tests may pass while security assets (e.g., cryptographic keys) still leak or persist in unexpected locations (debug ports, shared buffers) due to race conditions or incomplete policy enforcement (Speaker: Pete Marr).
  • Post-Silicon Liability: Failure to detect hardware weaknesses (like Spectre-class vulnerabilities) before tape-out exposes companies to severe financial and reputational liability, as fixes after silicon fabrication are costly and difficult (Speaker: Leon Brown).
• Management Tone on the Future:
  • Urgency and Shift in Paradigm: The tone conveys a critical shift from "proving the design works" to "proving the design is secure." Management asserts that the industry must assume attacks are now automated and rapid, requiring a fundamental change in verification methodology before tape-out.
• Miscellaneous:
  • Technology Capability: The speakers state they cannot provide a timeline for future product updates or revenue growth, as the webinar is a technical deep dive into current capabilities (PsiQt) rather than an investor relations update.
  • Customer Adoption: Arteris notes increasing uptake in the federal, automotive, and commercial AI sectors for their security assurance solutions, with a specific mention of Arm expanding their usage of these solutions for new designs in the near future (Speaker: Leon Brown).