Technology and Product Webinar - MICRON TECHNOLOGY INC

Financial Performance:

• No specific Q4 financial results, revenue figures, or margin percentages were disclosed; the call focused exclusively on technology strategy and product roadmaps rather than quarterly financial reporting.
• Management highlighted the "trade ratio" (wafers required per unit of output) as a critical cost metric, noting that advanced solutions like Vertical HBM and Vertical Edge Inference Memory (EIM) have significantly higher trade ratios compared to standard DRAM due to stacking complexity and bandwidth requirements.
• Emphasis placed on "cost-per-bit" efficiency as a core driver for future scaling, particularly with the transition to Gen 11 NAND and One Delta DRAM nodes.

Guidance and Future Outlook:

• Micron anticipates a sustained memory shortage for the next two years, with no expectation of supply-demand balance returning within that timeframe.
• 2027 Roadmap: High-volume manufacturing (HVM) ramp for "One Delta" DRAM node (providing mid-20s% bit density improvement) and Gen 11 NAND (400+ layers, 1.5x I/O speed, wafer-on-wafer bonding) scheduled for the second half of 2027.
• Long-term R&D: Announced a $10 billion investment over 10 years for Micron Research Labs to explore future compute systems, alongside increased focus on Albany Nanotech for advanced lithography (EUV) and Micron Ventures ecosystem expansion.
• Innovation Pace: Projecting a 10x improvement in DRAM performance per unit of leakage current by 2030 through optimized CMOS logic variations.

Business Segments and Product Lines:

• HBM (High Bandwidth Memory): Currently in HVM for HBM4; HBM4E ramping next; launching "Vertical HBM" (stacking memory directly on processing units) to maximize bandwidth and co-design with customers.
• DRAM: HVM for "One Gamma" node; "One Delta" node ramping in H2 2027.
  • LPDDR6: Industry-leading implementation optimized for data centers and mobile, offering >35% power improvement over LPDDR5.
  • DDR6: Delivering 2x bandwidth over DDR5 for data center servers.
  • High-Capacity Modules: Sampling 512GB DDR5 RDIMMs; targeting 1TB RDIMMs as the industry's highest capacity solution.
• NAND: Gen 11 NAND will double bit density vs. Gen 9 with higher I/O speeds.
  • AI-Class NAND: Developing High IOPS (SLC-based) and High-Bandwidth variants (TSV stacked with logic) to serve edge and data center AI workloads.
• Edge AI: Launching "Vertical Edge Inference Memory" (EIM) – stacking low-power DDR on logic – to address thermal and power constraints in autonomous vehicles and robotics.
• SSD: PCIe Gen 6 controllers in mass production; leveraging AI to accelerate SSD controller design by 2x and product development by 60%.

Market and Competitive Landscape:

• Market Position: Claiming "strongest position in history" for technology leadership, citing 4 consecutive DRAM leadership nodes, 3 HBM generations, and 3 NAND leadership nodes.
• Competition: Explicitly rejected the viability of "4F-squared" DRAM scaling beyond current limits, asserting that 3D DRAM is the necessary future path due to physics constraints, distinguishing Micron's roadmap from competitors pursuing 4F-squared.
• Ecosystem: Deepening co-innovation partnerships with hyperscalers (e.g., Meta) and startups (e.g., Weka) to co-design memory IP and logic IP for custom HBM and base dies.
• Demand Drivers: AI training and inference are driving a shift from mere "bit count" to "capability," with memory becoming the primary system bottleneck for AI performance.

Risks and Challenges:

• Thermal Management: Significant complexity in managing heat for Vertical HBM and Vertical EIM products, requiring advanced heat spreaders and thermal-aware co-design.
• Physical Scaling Limits: Planar DRAM approaching atomic limits; planar NAND scaling halted years ago, necessitating complex 3D stacking.
• Manufacturing Complexity: Transition to wafer-on-wafer bonding, hybrid bonding, and high-density stacking introduces cost and yield challenges that must be managed carefully.
• Supply Constraints: High demand for advanced memory combined with limited capacity (shortage) may constrain the ability to meet the "insatiable" demand for AI workloads.

Management Commentary and Tone:

• Tone: Highly confident and optimistic; management described the current period as an "unprecedented" opportunity with the "farthest extended roadmap" in company history.
• Strategic Focus: Emphasized that "memory is the limiter" in AI systems and that Micron's strategy centers on increasing bandwidth and capacity simultaneously.
• AI Integration: Highlighted the internal use of AI to accelerate R&D, reduce manufacturing variation, and speed up silicon-to-tape-out cycles by 2x.
• Customer Collaboration: Reiterated a shift from transactional sales to deep "co-innovation," where Micron works with customers from physics-level design through to high-volume manufacturing qualification.

Analyst Questions and Answers:

• Workload-Specific Memory: Addressed concerns about memory becoming too expensive (BOM share). Management confirmed that while customers will optimize for specific workloads (inference vs. training), memory content and bandwidth will generally increase to maximize system performance; there is no trend toward reducing content, only optimizing architecture.
• 4F-squared DRAM: Clarified that 4F-squared offers no density advantage over 6F-squared if capacitor pitch is constant; Micron believes physics prevents viable scaling beyond current nodes on 4F-squared, making 3D DRAM the superior path.
• Compute Racks & Networking: Confirmed that memory-intensive configurations will vary (dense vs. high-bandwidth) depending on rack topology, but all will require advanced memory solutions.
• HBM Base Die Nodes: Confirmed that custom and standard HBM base dies will utilize advanced foundry nodes (logic process) for power and performance optimization, particularly for HBM4E and Vertical HBM.
• PIM vs. Vertical EIM: Discussed "Processing in Memory" (PIM); Micron notes it is in flight but views Vertical EIM as providing substantially higher bandwidth and performance for high-end edge applications by leveraging a base die with logic IP, offering a more flexible performance-to-power spectrum.

Other Key Points:

• Hybrid Bonding: Identified as a critical enabler for Vertical HBM, required to achieve necessary interconnect density and thermal performance for bandwidth scaling.
• Token Efficiency: Framed memory evolution around "tokens per watt" and "cost per token," driving the need for higher capacity and bandwidth to lower AI inference costs.
• Vertical HBM Architecture: Described as a parallel path to standard HBM, integrating memory directly on top of XPU to eliminate interconnect bottlenecks, distinct from simply stacking more HBM layers.
• Roadmap Visibility: Expressed higher confidence in the next several years of scaling for both DRAM and NAND than in recent historical periods.