Technology and Product Webinar - MICRON TECHNOLOGY INC

Hello, everyone. Thank you for joining us and welcome to Micron's Technology and Product Leadership webinar. After today's prepared remarks, we will host a question and answer session. If you would like to ask a question, please press star 1 to raise your hand. To withdraw your question, press star one again. I will now hand the conference over to Satya Kumar, Corporate Vice President, Investor Relations, and Treasury. Satya, please go ahead. Thank you, Christine, and welcome to Micron Technologies webinar on technology and product leadership for the AI era and beyond. On the call with me today is Dr. Scott DeBoer, President and Chief Technology and Products Officer. AI is driving significant changes in memory and storage requirements, and we're excited to have Scott here with us today to provide investors a deeper look at our technology roadmap and innovation strategy. Before we begin, I want to remind everyone that today's discussion includes forward-looking statements, including regarding our technology and product roadmaps, investments, and business opportunities. These statements are subject to risks and uncertainties that could cause actual results to differ materially. Please refer to our SEC filings for a discussion of these risks. With that, let me turn it over to Scott. All right. Thanks, Satya. And good morning, everyone. Thanks for joining us today for this pivotal moment in our industry where AI is really changing so rapidly and redefining computing. Today, I'm going to talk about how Micron is shaping that future and making it real at scale. The next era of AI will definitely be won by advancing memory, storage, and compute together. and Micron's in a unique and strong position, leading in bandwidth, capacity, power efficiency, reliability, and increasingly focused on supporting our customers to execute their extremely complex systems going forward. So today, I'm going to talk on a number of points and try to give you a feel for how Micron is positioned. And definitely, we are in an unprecedented position in time with an opportunity for memory and storage in particular. And through this first stage of the AI transformation, Micron has executed and delivered extremely well. Micron's technology leadership really is foundational, and I'll talk today about that foundation and how it's going to evolve through time. Truly, the differentiated industry leading products that we have today and that we'll have going forward are all built on a core technology leadership position. And that's a focus for Micron going forward. In addition to the technologies that we're creating in our products, AI also accelerates our team members' ability to innovate and execute. And this is a major focus of Micron. And I think we are leading the industry and our implementation of AI products and technology capabilities across our whole development roadmap, really from starting physics through design through ultimately reducing variation in manufacturing and using smart manufacturing across our ecosystem to ramp faster than we've ever done before. I'll also touch today on our longer horizon R&D investments that we're focused on to really enhance Micron's future competitiveness. We're making substantial investments and really changing the way that we'RE looking at longer term R&D investments from many, many aspects, and I'll give you a feel for some of the things that weRE doing there. I've said before several times, and we've emphasized that co-innovation really is a key part, and it's very different today than it was in the past. Micron's co-innovation with our partners, both suppliers and customers, really are a core piece of how we deliver these leadership solutions and help Micron position itself with the optimal memory and storage to support our customers' next-generation products. All of this adds up to Micron being positioned to really extend our technology and product leadership the next decade, and we're uniquely positioned, I think, with the strongest opportunity that we've ever had and probably the farthest extended roadmap in terms of technology and advanced products that I've ever seen in my career. Truly a unique period in time. so first just to touch on a few background pieces relative to where we're at today the products that we've we have focused on and are underpinning micron success up to this point really are have been training focused and through the first part of this inferencing wave and really there's a wave of of ai increases in memory demand that continually come at us and we're still in the early innings of the adoption and the evolution of the AI systems. And each of these is going to drive significant changes in usage and demand on the memory products, not just in terms of bits, but definitely in terms of capability and what type of products in the memory and storage area that we built. Truly an interesting and unique period of time where Micron's technology leveraged or technology position can be can be leveraged to really position the company stronger going forward when we look across the architecture that supports these waves of of ai transformation micron's portfolio really goes across all of them it goes across all of us through time with different types of products different types of innovations that we focus on with our customers and really spans the portfolio from HBM today in terms of ultra high performance memory evolving to custom and then future vertical HBM solutions that I'll talk about today supporting our customers needs at the at the very highest performance levels in addition to that we've seen over the past couple of years really the importance the growing importance of high-capacity DDR modules and the the exceptional performance that's provided by low-power DRAM in the data center. And that continues and expands through the next several years. And our focus, as I'll talk about today, is on making sure that the next generation of both DDR and low-powered DRAM modules are truly optimized for what's coming ahead in the AI world. We've had great progress on the SSD front in terms of data center SSDs. The business and technical teams have really delivered strongly over this past couple of years. And that's been noted in our earnings calls and in several other public disclosures relative to our progress on data center SSDs. Today, I'm going to talk a little bit more about what's next in our focus really in enabling AI class NAND, which is higher performance, different varieties of higher performance NAND products that support opportunities that our customers are looking at in terms of leveraging that to get better and better performance out of the end systems. And finally, high-capacity SSDs, as we leverage our technology leadership and our cost structure, cost-per-bit structure of our advanced nodes, higher-capacity SSDs continue to be a focus and continue to Bea a key important point for our data center customers. But memory is not all just about data center. And the technology and AI implementation into multiple other spaces is critically important as well. And a few of those on this slide noted in terms of autonomous vehicles, robotics, and, of course, AI PCs and mobile, all evolving with AI and all driving unique requirements from the memory technology. So, what is great AI technology for data center may not be optimized and truly is not optimal for these other edge applications, and we're focused on new types of products across all these edge spaces and looking at the opportunities with our customers to build optimal memory across each of these different types of non-data center focus areas going forward. So, if we look at that first wave, we've had tremendous success and building on core technology leadership to enable a number of industry-first and best-in-class products. And these really span across the product portfolio that I mentioned on the previous slide, driving LPDRAM in unique ways to have industry- first and sole-source positions with LP-based products. the SO-CAM modules leveraging LPD-RAM, SO-Cam 2 modules leveraging LP-D-Ram have come out and really been a key driver of that part of our business. We've been a leader, of course, in SO- Cam 2 and driven the highest densities available in the market with that. On the data center SSD side. We've leveraged our technology leadership and really a long-term partnership, both with customers and an internal focus with our SSD team to enable PCIe Gen 6 first in industry and deliver it into mass production. Micron's come a very long way from just four or five years ago in terms of our position in really being at the forefront of data center SSDs. And that's something that we're very focused on, and I'll talk a little bit more about today how we're going to continue that path. This slide highlights a number of other industry firsts that are of critical importance, and of course, HBM4 strength is one of those, and as we've mentioned, we're in high-volume manufacturing with HBM 4 now, very successful product ramp, and a world-class product there, and moving on to HBM4E that I'll talk about in the rest of the roadmap as well. And then one of the most recent accomplishments noted on this slide is our high-density RDMs. We've sampled a 512-gigabyte DDR5 RDM recently. It's the world's first module of this sort with exceptional performance and positioning for high-density module optimization and usage by our customers, again, coming from a position a number of years ago where we were not in the leadership role and have put significant focus over the last several years in making sure that every aspect of this product portfolio is intentionally positioned to take advantage of of opportunities with our customers no question as we look at the waves of of ai um coming coming towards us and inferencing raises the bar on memory technology and memory technology is is fundamental to how ai works and and i think it's it's relevant here to just talk about all all the touch points as we go through what happens and how in-memory evolves into this and engages into the ecosystem, starting with just the example of a simple prompt and the context of information being stored in DRAM and coming from storage SSDs for that prompt holding the background information. And then the LOM inference, really reading that prompt and utilizing low-power DRAM to optimize energy efficiency and working with capacity to drive the prompt into understanding what the answer is to that question. And then going through a number of calculations through the KV cache and then really having the HBM engine drive the data back and forth with the GPU to get to that answer, which is then generated one token at a time. And those tokens live in memory, and memory is the foundational piece of the ultimate performance of this system, really driving and living in the memory. So the position of memory has never been more important as it is relative to AI today, and this opportunity just keeps getting bigger as the models and the capability continue to grow. So when we look at the pieces of how memory drives and continues to scale to meet these waves of oncoming AI opportunity, we have to foundationally continue to scale memory. And I'll talk today about our confidence in continuing to be able to drive memory technology to meet this challenge. Absolutely, Micron has a history of successful scaling and I'll a little bit about some of the sustained technology leadership we have on the next slide. But this slide just highlights the foundation that we're building on. And it is a little self-serving since 1995 is when I started at Micron, so I made the graph start in 1995. But 22 nodes of DRAM technology since 1995 to today, ending in our one gamma node, which is a very high-volume leadership node in the industry today. And we're building on that to really ramp this next generation of AI products over the next year. That'll be our main running node. And for context, this graph represents about 400x, as stated here, more bits on a DRAM wafer since 1995. When you look at this one gamma node, which is the workhorse of Micron on the DRAM side now, positions itself with kind of a unique, understandable explanation for how small it truly is in fitting more than 1,500 capacitors across the width of a human hair on this node. Micron's leadership, as we've talked about in multiple forums, has been sustained over the past multiple nodes, really four nodes of DRAM consecutive leadership, three nodes of HBM generations in power leadership, and NAND focusing on delivering three consecutive leadership nodes from G7 to G9. Today, I'm going to talk about what comes after these, but this accomplishment really is a result of many focus areas across Micron of our outstanding technology and innovation team driving technology across many fronts and executing flawlessly over a number of years to position Micron with this leadership. And we absolutely don't take this leadership for granted. We're focused on making sure that this execution continues and that we truly continue to leverage this global world-class team to enable leadership in DRAM, HBM, and NAND going forward. The last time I'm going to use this slide, I've used it at a couple of external events, but I really like the illustration of the pace of innovation in memory relative to other things. And as a look at a Porsche from 1995 with 270 horsepower and cost about $60,000 and 23 miles per gallon. The illustration of what the pace of the memory industry versus the automotive industry really would be if automotive had matched the pace of the DRAM industry. This vehicle would now have about 2.7 million horsepower, cost $5, and have 23,000 miles per gallon if the auto industry had moved as fast as the DRM industry. So really a unique piece of how fast things move in the technology cadence across memory. Another interesting piece here before I shift to the technology roadmaps is really the piece of recognizing how outstanding the performance of HBM4 truly is. And this just gives some context for exactly how powerful this device is, how complex this device is. With one HBM4 stack now delivering 2.8 terabytes per second of bandwidth and looking at the total internet bandwidth in the world. Right now, this is across the internet Google data. worldwide internet bandwidth is 282 terabytes per second total so about a hundred hbm4 stacks can match the the worldwide uh internet bandwidth okay but as we all know um memory is currently a focus and as we've discussed memories at the center of ai and it is absolutely the the limiter in terms of ultimate system performance and capability at this point, and we take that very seriously. As memory has become the AI bottleneck, our focus on making sure that memory capability continues to evolve, memory architecture continues to evolve. Both of these things must happen, and I'll talk about our roadmap to deliver that. Ultimately, memory shapes AI capacity and performance and cost per token, so our focus on working with customers to make sure that that we deliver the optimal product solutions to make that happen so if we look at now stepping into microns technology position and again it really is a price of entry situation technology leadership is absolute absolutely underpins our ability to deliver the differentiated industry leading products it's been core to the previous ones or the past couple years and it will continue to be really that key technology foundation that underpins the next set of products that are coming along. So I'll step into exactly where we're going with core technology. So first just a general point on memory technology and the evolution. On the DRAM side, planar DRAM has been scaling for you know decades and Micron has been in a strong position as mentioned it's foundationally shrinking the the xy dimensions of the DRAM of course it's a very vertical process now so there's 3d aspects to it but we don't call it 3d DRAM at the moment it is it is just a function of making the chip the cell smaller and smaller DRAM is nearing atomic limits at this point although we have confidence in several more planar nodes. We are very focused on making sure that we introduce 3D DRAM at the optimal time from a cost and performance point of view. So our intention, as I'll talk more today, is truly around making sure we have 3DDRAM prepared and that we'll implement it at the proper time for the market. On the NAND side, I think everyone is familiar that planar NAND ended scaling in around mid-2015-ish timeframe. Micron scaled that to about a 16 nanometer planar node before it wasn't capable of scaling any longer and successfully transitioned into 3D NAND, which was a function of primarily Z-scaling, adding more layers to 3D manned across multiple nodes. The current industry direction and Micron's direction is scaling in both by adding layers, but also by shrinking the cell dimensions. And that complexity will continue to provide benefits in terms of cost structure and performance over the next several nodes. And then we'll be looking at future alternatives, which I'll talk a little bit more about on some upcoming slides. But again, confidence in both the DRAM and the NAND scaling path. And I think from a visibility point of view, have more confidence in the next several years of scaling on both DRAMs and NANDs than we have in quite some time. On the DRM roadmap, we have multiple, and I'll go through the picture of exactly where we're at. As I mentioned, the one gamma node is in high volume manufacturing today at the basis of all the key products that are coming out in the next 12 months and very confident in that industry-leading node. It was the node we introduced EUV at first, and that's been a successful introduction and our manufacturing team has done an outstanding job of ramping that and leveraging that capability. On our one delta node, which I'll talk about starting a little bit more on the next slide, is the node that we're focused on in Boise, but it'll be U.S. manufactured as well as in other facilities. And this technology is coming along rapidly, and our intention is to ramp that into volume in the second half of next year. And then beyond that, we have a number of nodes in progress, and just we'll talk a little bit about that path. Our one epsilon node leverages wafer bonding and optimizes the big growth and technology capability to deliver truly unique solutions in the AI space. And that's well underway. And then pathfinding, we have going on both early development for our OneZeta node, OneZета Angstrom node, and our Ada Angstrom nodes beyond that, bringing in combinations of high-end AUV, new materials, and a number of other innovations to continue this planar roadmap successfully over a number of years. So lots of confidence, high confidence in this DRAM roadmap through this period of time. For reference, we have looked at and investigated 4F-squared DRAM really over the past two decades, micro-invented 4F squared DRAM. The path with 4F square DRAM has always been an option through time. And we've evaluated it and not pursued it due to increased complexity and cost through this past two-decade period of time. But development has continued continuously through there, and we've had a number of prototype products to compare through time. Two challenges are holding Micron or have convinced Micron not to go down this. One is that the scaling path is not viable beyond a certain point. So, there's no actual benefit to going down that path. The second piece is there's a bit of a misnomer about what actually drives the bit density per wafer on DRAM. And foundationally, it's important to understand that the capacitor pitch, the capacitor size and dimensions is actually what sets the DRAM bit density, not whether it's 6F squared, 4F squared 8F squared. Everything is optimized around the capacitor pitch. And then underneath, actually, you can optimize with 6F squared or 4F squared and fit those for a given capacitor dimension, however you'd like to. So it's really about optimizing process complexity, process margin, and cost relative to a given, a given capacity pitch, which is the foundational element of how we built DRAM. When we look at 3D DRAM, we have that on the roadmap, as I mentioned, and it's shown here in between one Zeta and one Ada. But in reality, this is a parallel path, and we'll implement it in a fashion that is ideal for cost and complexity and device performance. And the timing of it will depend on micron business decisions from a technology and a product point of view it'll be ready to implement in the optimal time as we've done with previous major technology transitions. Okay, a little more on our OneDelta node. This is focused in Boise today. The fifth consecutive industry leadership node is our anticipation with this ramp in 2027, second half. A few early mentions on capability of this node. This is going to provide in the mid-20s percentage bit density improvement focused on optimizing costs while providing the densities that are required. The performance will be optimized to meet our HBM-5, our vertical HBM, and our vertical EAM products, which I'll talk about in more detail on some upcoming slides. But this node really is optimized for AI, and it's aimed to deliver the kind of power and bandwidth that is going to create those leadership products that I talked about we've done before and will enable in the future. So this ultimately is going to be a great node. The picture in the middle is a picture of the cells on this one delta node, and we're very, very excited about this node ramping over the next year. When we look at, besides the node itself, we look at the DRAM CMOS logic roadmap, which over the past several years has been what we have leveraged to create differentiated products so we when we look at DRAM CMOS it is not one CMOS for a given node we within a given node for example in beta we will have multiple variations of CMOS that we will implement into specific products on that node so optimized optimized for LP performance or optimized for HBM performance will have CMOS that meets the requirements to deliver to the specifications that our customers need this has become a very significant focus for micron over the past seven years in enabling the right technology for the right time and we've gone through a number of different variations that we have capability for now, these have created from 2020 through 2030 projection, will create about a 10x improvement in performance in terms of drive at a given leakage current to enable the kinds of performance that we need. So, at multiple nodes of power and performance leadership and a roadmap that continues to deliver that through time and will become increasingly complex as we go forward with different generations of both plain or high-K and then 3D CMOS to support the needs. When we look at DRAM based on this technology and the products that we are delivering in the next generation, three that I want to highlight today are our LP6 for data center and mobile, which has been a major focus from our design teams, doing a great job of putting together industry-leading products here that will leave the industry in power with 35% improved power versus LP5 and more than 35% on some densities. So, big, big push on LP6, which is going to be a key memory type, both for mobile, obviously, but increasingly important for data center. On the DDR6 front, Micron's leader 6 implementation, lead partner with key customers to deliver this higher bandwidth 2X versus DDR5 that can be leveraged across data centers for server applications. So lots of focus on these transitions to LP6 and DDR6. And then in the meantime, I had mentioned the 512-terabyte RDM that we announced recently. The next generation will be delivering a 1-terabite RDM for the industry's highest capacity RDM product. So, many different focus areas for specific customers across our DRAM product portfolio. When we look at HBM, we're building on our HBM leadership from the evolution from standard HBM like our HPM4 product today to what we've talked about in terms of custom HBM. Both standard and custom will coexist in the ecosystem depending on the customers. we are focused on this co-design element with our customers co-optimization with customers to implement both memory ip and logic ip into our base die to then deliver ultimate system performance with with the customers who want custom and of course we'll have high performance on standard hbm uh 4e for those customers that don't have custom design as we go beyond that that. We're focused still on custom HBM and standard HBM, but we will add in a product focus that's very important going forward, which we call vertical HBM. This is an implementation of memory capability directly on top of processing units and is a key element of our customer partnership going forward in delivering this solution, which provides ultimate bandwidth in combination with co-design and also still utilizing HBM around the edges of, in many cases, of the XPUs. So supporting that execution is a number of advanced packaging innovations, all required to deliver the HBM performance and the vertical HBM performance that we see as necessary with customers. Interconnect density is really the driver of our requirement and driver of many of the technology requirements. Ultimately, hybrid bonding technology is a major focus for Micron. Our capability is strong. This still needs to evolve through time to be prepared to implement it in a high volume manner. But ultimately the driver of hybrid bonding winds up being interconnect density so the the pitch of the pads in order to get bandwidth requires closer and closer connections spacing closer and closer spacing between connections hybrid bonding is the solution uh to that technical problem in addition to the well-publicized thermal benefits of hybrid binding ultimately you can't build products with a certain level of bandwidth without hybrid bonding. So it's a major focus for Micron, and we intend to be leaders in that space. Stacking technology is still key, and ultimately there will be implementations going forward of higher and higher stacks because memory capacity does play a major role in driving token costs down and in ultimate system optimization. So this particular picture in the middle of the slide indicates 16 high HBM stacks built both with micro bumps on the left and with hybrid bonding on the right. So different implementations of 16 high products and ultimately the hybrid bonding in this case is beneficial as mentioned for both bandwidth enablement and thermal improvement. So, stacking technology continues to be a major technology capability that Micron's focused on leading, and it's in a strong position at this moment. It becomes an even stronger requirement as we look to the transition or the inclusion of 3D vertical HBM integration products in terms of enabling, as I mentioned, the tighter interconnects and thermal management. Thermal management becomes even more important as we look at vertical HPM products, which have to be optimized around heat structure, both of the base die, heat flow, both from the base dye and from the XPU that the product is mounted on. So significant complexity requires very complex integration with our customers, co-design, and the designs have to бытьhermally aware. It's a key piece. One example of an innovation that Micron has implemented in the future in our designs now is the heat spreader, which takes a position on the HBM cube over the hottest part on the HPM base die and effectively serves as a chimney for heat from the base up past the HPM cube. So, this innovation is a key piece in the positioning and the design of that innovation to cover that fire area of the base die as a key enabler going forward. Token efficiency focus is an urgent requirement, and it brings about a diversity of different types of products. And I'll hit on just a couple of these right now, but they're important ones. Both the vertical HBM that I've mentioned, the vertical edge inference memory, both have commonality in terms of structure, in terms of the packaging requirements, the thermal requirements, and the need to co-design with customers. As you look across this timeline of these products coming in, one thing to note is trade ratios continue to increase as you go from left to right. As these products come in, the trade ratios continue to be stressed in terms of the number of wafers it takes to build HBM, vertical HBM and vertical EIM relative to building standard DRAM bits. So that pressure remains through this roadmap. When you look at the different packaging requirements for vertical edge inference memory versus vertical HBM, while the structure looks similar in terms the packaging capability needed, The products are optimized in different ways, where vertical EIM has lower bandwidth requirements, but substantially more sensitive to power requirements. So it's really designed in a way to get bandwidth capability to drive these edge products in an effective way, but optimized for power. While vertical HBM, as it is implemented in parallel with other varieties of HBM. It comes in with huge bandwidth benefits, so it's very bandwidth focused and improves in capacity over time, but really bandwidth focused is the deliverable of the vertical HPM technology. I'm going to shift over to NAND. We've been in a very strong position with our Gen 9 NAND. And this leadership is going to extend with Generation 11. And this is a significant leap. We have optimized this memory. We've actually gone back and ensured that this memory is optimized for the AI products of the future. And intentionally, which is why it goes from Gen 9 to Gen 11, we've made substantial improvements that this node really brings relative to any prior NANDs. A few of those are doubling the bit density versus Gen 9 NAND, but then also a 1.5x IO speed target and then focus on data transfer energy and really bringing that down relative to G9. So this G11 technology is the world's most advanced NAND. It will ramp in the second half of next year. Also, it's based on wafer-on-wafer bonding technology, which is like I had described before. We had mentioned we'll bring in wafer to wafer bonding at the right time when it's cost-effective and it brings in capability that's important for the product specs at the time, and this is the right timing for that technology. We'll be at more than 400 layers, and we'll get more specifics on that next year, closer to the launch dates. But as mentioned, it will be ramping in the second half of 2027. And then beyond G11, we have a strong roadmap, not going to go into great detail on it today, but really focused on new materials, densifying the cell architecture, and continuing to focus on that XYZ scaling going forward. So big generational leap with our Gen 9 or Gen 11 nan technology rolling out and excited to see how that really underpins the ai focused products we have going forward when we look at those products going forward really two focus areas our micron's focus is to ensure that we are capable of meeting customer needs on a variety of different higher performance nan products and there's really two focused areas here one is on high ops high iops AI class NAND, which is SLC-based designs implemented in small blocks to design ultra-fast memory storage products. And this is a key piece that meets several emerging use cases noted here and really is a major focus for Micron in terms of getting these products out to market over the next couple of years. On the other side of this architecture and design path is high-bandwidth AI class NAND focused on other emerging use cases. And these ultimately are more costly and have to be implemented in partnership with customers in a way to ensure that they're meeting the mark and the cost point to drive the value proposition. But definitely enabling TSV stack NAND with logic-based eye to put closer to the accelerators. So not along the shoreline of the GPU, as we don't think that has merit, but along closer positioning points to the compute itself to make use of this high-performance NAND and the viability of that path. and then there's a number of looking at the segment view a number of different segments that utilize a combination of those two architecture choices as mentioned if you go from data centered automotive there's different cost sensitivity levels and different interactions with customers to determine which ones are appropriate and which ones we want to provide ultimately to customer demands next hitting on a couple of last topics. First on AI accelerating AI. So how we use AI across Micron to enable innovation and execution and really position our team members with all the tools to deliver industry-leading products going forward. And a couple of examples here just to highlight where we're at today. One on data center controller design. This is a demonstration that is confidently being executed right now, delivering this controller in two times faster pace from silicon to tape out. So 50% less time from our prior generation of SSD controller to the new controller utilizing a variety of AI tools. Second example, also confirmed now, is developing an entire data center SSD product. In this case, a little bit faster than 2x, 60% less time in going from the prior generation to the next generation, really leveraging AI-generated firmware, root cause analysis, enabling agents to do a significant amount of the core determination of product viability, and then optimizing around the path to make that product work. So besides those two examples, definitely focus on basic physics all the way to smart manufacturing, which are impacting every single engineering employee at Micron and making them more successful. The next couple that I want to highlight today are around R&D investments, really to enhance our future competitiveness and then a little bit about how we co-innovate with customers. So, first on the long horizon, R&D investments, we've announced several lately that are significant changes in how we've operated and how far we've looked out into the future. Definitely ramping up our micron ventures efforts and we've had some press on the increased capital commitment relative to Micron Ventures, focusing on strengthening the ecosystem engagement. Albany Nanotech are announced to focus on advanced lithography. They're really driving a high-end EV roadmap for DRAM in particular at Albany with our team there, focused on the next five to 10 years. And then the big announcement we did this summer on the 10 billion over 10 years focus on Micron Research Labs, really with Micron taking a broader position in long-term research outside of our current product roadmaps and shaping what's next for the memory and compute systems of the future. And we look at an example of how we combine that for customer advantage. An example of customer collaboration really goes from a good example with Weka and Micron here as is a company that we invested in from our venture fund and have built that into a partnership in supporting them and working out business arrangements with them to help them grow. So starting from an early investment to leading into business. So really interacting all the way from a startup like that to the focus with Meta, which is highlighted on this slide also, relative to LPDDR6. And we put out a white paper that was released this morning, really a great partnership there in optimizing LPDDDR6 for the data center and in partnering with them to understand how we take advantage of the unique server capabilities and higher reliability capabilities built into LPDDR6 and optimize that together. So really from startup through hyperscaler, engaging the customer interaction to improve Micron's future AI-related products. Overall, as a general point of view, really across our AI co-invention opportunities, We're co-imagining, co-designing, co developing, co validating and then delivering at scale. And this this opportunity is truly unique. It's very different than the way we interacted with customers even three or four years ago. But the opportunity to partner with customers to really understand from an early point of view what can be done with memory products, how customers can leverage that. and then ultimately building that into really having engineers working together on co-designs and solving problems together all the way to the point of getting that final qualification with the customer, co-validating it, and then, ultimately, ramping it in scale. Okay, so all the emphasis today hopefully has given a little bit more perspective on how Micron's position. We feel this is the strongest position Micron's ever been in, in terms of technology and product leadership. Partnerships with customers have never been stronger. Our connections into the ecosystem are growing, and we're going to continue to expand that, really in a unique position and a very proud position, but absolutely one where we're focused on future execution in this growing era of complexity and making sure that we can leverage AI to deliver innovation and execution at an even faster pace. So with that, I will conclude and I think we're ready for questions. We will now begin the question and answer session. Please limit yourself to one question. If you would like to ask a question, please press star one to raise your hand. To withdraw your question, press star 1 again. If there are any follow-up questions, please re-raise your hand to re-cue. We ask that you pick up your handset when asking a question to allow for optimum sound quality. If you are muted locally, please remember to unmute your device. Please stand by while we compile the Q&A roster. Your first question comes from the line of Vivek Arya with Bank of America. Vivek, your line is now open. Vivek Murthy Thanks for taking my question, and thank you, Scott, for the very informative webinar. My question has to deal with how do you think the end customers are dealing with the fact that memory is becoming a bigger part, right, some say half or more of the bill of materials. There is some talk of, you know, despecking and making memory more workload specific. So kind of the specific question to you is, do you see DRAM content becoming more workload-specific? You know, is it possible that when we look at inference workloads that the DRAM content might be lower or different than what it is in terms of training accelerators? Would that be a change from what was assumed before? So just how do you, in low customer interaction, see them dealing with this rising impact of memory? and would there be a change in inference versus training DRAM content? Thank you. Sure. Thanks for the question. So I think the starting piece to this answer, and I'll go into a little more detail, the starting piece of this answer is for a given system, memory content and memory bandwidth capability will make the system operate at a higher level as it increases. always there are ways to optimize for systems, but ultimately the system will work better with increasing memory content and increasing memory performance. So, as we work with our individual customers to create the products that fit with their system design through time, they will, of course, make decisions relative to what the minimum system requirements are, and they'll optimize relative to, you know, shipping their products and their business as well. But the underlying piece is their product will work better with the highest memory bandwidth and highest memory content. So eventually, this will, you knows, evolve through time. And, you Know, as we've said, we're focused on both creating, increasing our supply with all the investments that Manish and we've talked about through earnings and other times, public times, but also through making sure our products can deliver higher and higher bandwidth through a number of these things like vertical HBM and vertical EIM so that the systems can be optimized. And for sure, if you look across the space of products, you know, edge inference, mobile products, different kinds of small model products will have different memory optimizations. But in general, the underlying piece here is memory is still core to AI capability and AI system capability and will continue to press to, customers will continue press to optimize that. And inherently, more memory does equal better system performance. Your next question comes from the line of Timothy Arkery with UBS Securities. Timothy, your line is now open. Thanks a lot. Scott, you said that there's no viable scaling path for 4F squared. Can you just double click on that? why would, you know, we're hearing other competitors pushing this and why would they want to do that? And like, why do you think that there's no scaling path forward? Is it like an equipment readiness issue? And maybe do you Think that there will be a time for four F squared? And if so, when? Yeah, so I can't comment on why other customers or other suppliers would do things I can only say from our investigation of this technology over the past couple decades. First off, it's a bit of a myth that 4F squared actually provides anything versus 6F squared. It's the capacitor pitch that defines the DRAM. You can build the cells, the transistors underlying in different ways, but they still have to fit under the capacitor pitch which sets the DRM. So, some of that is just kind of smoke and mirrors in terms of talking about 4F square versus 6S squared. Now, when you look at a scaling path, you can go back a few nodes and absolutely 4F Squared can be built, back a few notes, no question about it. It's more complicated, it's more complex, it is more costly, but you can do that. When you look out from Micron's point of view as the leading edge technology company, when we look at scaling 4S Squared beyond where we are sitting today, it' s physics, there is fundamental problems with 4S squared scaling that ultimately will lead to 3D DRAM coming in instead of 4S square. Your next question comes from the line of Ben Bajoran with Creative Strategies. Ben, your line is now open. Hi. Thanks for taking my question. So, Scott, just a quick one on how you think about memory roadmaps as it relates to next-generation compute scaling for racks, meaning more the compute domain that everybody's talking about, So not just having one rack to run a model, but networking those together to two or three or four and how that might impact memory when they can run larger models within Compute RATs networked as one compute domain. So I think there's going to be a lot of different configurations of compute depending on the customers. And our focus is making sure we have the products that can optimize in any of those domains. As we've said, the next few years, we don't see a period of time where memory is not going to be in short supply in the next two years, as Sanjay said, and we actually don't see a time when it comes into balance. So our focus, whether it is in these different kinds of configurations or in the leading edge configurations of data centers today, or even the edge in other devices, that we create the types of memory products with the bits that we have that optimize the solution for those customers. So I think there are going to be different kinds of solutions. They are all going to be memory intensive. And whether our optimized LP solutions, LP6 solutions, or DDR6 solutions are required in bigger volumes for some configurations or other configurations require high density or medium density products or more HBM. I think we just are going to leverage our close collaboration and connections with customers to be sure we deliver, we have the products that they need for how they're going to build their racks. Your next question comes from the line of Srini Pajari with Royal Bank of Canada. Srini? your line is now open thank you thanks scott for the uh doing the presentation uh my question is on the base dive for hbm i know you guys talked about moving to a foundry process node uh in the future um i'm just curious you know uh i know he didn't announce exactly what process node but it does seem like it might need an advanced process note going forward and nvidia talked about potentially moving the memory control into the base die. So if you could talk to us about what makes potentially the advanced process node necessary for the base dye. And then as you go vertical, do you see anything changing as far as the base is concerned? Or do you think that the advanced process is still kind of necessary depending on, I don't know, what kind of functionality might you know uh i guess you know get into uh base die versus you know the the gpu xpu in the future but when we go vertical just trying to understand um how you know you see the roadmap going forward sure so um to start with the the base die in the custom sense is um is absolutely a decision jointly with our the customer that we build the custom product for so in the example that you know actually I won't use a specific customer for example but if you if you when we co-design a base die and the certain logic elements that are desired to be put in that base die are generally an offload from GPU circuitry anyway onto the base die to put it closer to the memory. And so, the best leverage is to utilize the advanced node that's appropriate for the customer. We have flexibility generally to a certain extent to optimize the memory IP around, certainly around a more advanced node, but we would optimize it around the most cost-effective node that meets the performance. And going forward, as we said, we're on both Our standard Jetix design products and our custom products will be using Foundry nodes for both those base dyes. And we haven't stated what nodes we're using, but we're doing advanced nodes for for both to enable capabilities. Really, it's around power and capability into the base dye. So, as we've talked about, and I think I talked about this time last year, you know, for HBM-4, optimal power and performance didn't require that. You know, some competitors used it, our HBM4 didn't, and it has power andperformance strengths, as We said it would at that time. But for HBM4E, the performance, the speed, and the power optimization does require more advanced CMOS. So when we look out to vertical HBM, it will, again, have functionality in the base that connects directly to the GPU. And it'll provide, so it will still be at advanced nodes in the bass on vertical HPM. And it will have increasing functionality in that base die that can be leveraged there that connects directly to the GPU. Again, optimizing for quality, certainly quality and reliability of the VHBM product itself, but also optimizing for ultimate system performance, power, and leveraging advanced silicon to optimize the overall efficiency of what's on the accelerator chip below it. So, you know, moving what makes more sense onto the base die will still be a reality in vertical HPM timeframe as well. Your next question comes from the line of Daniel Newman with Futurum. Daniel, your line is now open. Hey, Scott. Thanks for taking the time today. I thought, You know, your slide where you showed sort of the AI increases on memory demand across training inference and agentic and then physical really told a very interesting story about sort of how Micron needs to both align and be more strategic with its partners in order to scale. But in order to meet what we expect to see continued growth across all these areas, across inference, agentic, and physical AI, what are some of the key areas of innovating, partnering, and building processes, both serial, parallel, that are going to enable you to keep up and deliver on sort of this insatiable demand that continues to grow? Yeah, that's a good question. Thank you. And definitely one that we've put a lot of focus into. So I think a couple things that I would point out is, one, although I only had one slide and a couple of examples on AI across our execution process, it is a major focus across the company. And that improvement of 2x timeline, you know, 2x shorter time to execution from innovation to high volume manufacturing, that is a key piece that we're well down the road on and is a major focus, but also a keypiece that we are depending on to increase our bandwidth and being able to cover the kinds of solutions coming at us from, you know, the whole ecosystem. Second piece is very focused and targeted product development in alignment with customers. And then in parallel on the technology front, enhancing our partnerships with key suppliers to make sure we're delivering specific capabilities. So, you know, whether it's across lithography areas or across packaging, hybrid bonding enablement, or, you know, film processing, different things with key partners that we have need for enablement and we can see what to deliver certain aspects of the products our customers need, we're strongly focused on deepening those partnerships. So, all the way across our supply chain and then up to our customers, making sure that we just focus very extensively on execution of this wide variety of things coming at us. And the bandwidth that we have across our engineering team increases substantially through the use of AI tools. Your next question comes from the line of Atif Malik with Citi. Atif, your line is now open. Thank you, Scott and Satya, for putting this together, especially the 3D DRAM versus 4S Square roadmap update. My question is on the physical AI or near memory where Micron is also taking a different approach with edge inference memory, EIM, which involves stacking low-power SBDDR on top of the logic die versus peers processing memory, which embeds computing units inside the memory. Scott, can you talk about the merits of your approach versus peers? Well, I can say that actually we have both product directions in flight. The performance of, It's a bit of a balance. When you look at processing and memory, there are certain capabilities that can be built in cost-effectively into LPD RAM. That balance and the system complexity of that is one set of considerations that we work with our customers on, but absolutely can say that we have processing and summary solutions in flight and in discussion with customers as well. The performance that we get from our vertical edge inference memory is just substantially higher. So, it reaches a point where the customer needs more bandwidth than can be accomplished through standard PIM type capabilities. And then a capacity that is also beneficial in these edge opportunities. So, you know, it again is, and we can also reach lower powers. Because of the use of a base die with LPE and the logic and memory IP that can be built into that base die, we could have a substantially higher performing product for vertical edge inference memory than we can with standard payment side of an LPE. So, it really is down to the customer interaction and customer collaboration to what type of solution benefits them most. And then we optimize the memory around that. Edge inference memory can provide a higher point of performance, which I think I had a few examples on the slide. But that can be tweaked with cost structure depending on how far the customer wants to go in terms of how much bandwidth and how much power. There's really a spectrum all the way from those numbers of sub-Picojoule per bit kind of powers and those bandwidths that are good enough for edge devices. The spectrum really goes from there all theway up to HBM. Since the structure is similar, it's more about segmentation and design of the DRAMs than it is about the core technology. The core technology is largely common. It's more of a design element difference between that edge memory and the vertical HPM, and we can optimize anywhere in between there, depending on the customer need. So it's really a platform that can be leveraged to meet different kinds of applications. Our last question comes from the line of Mehdi Hosseini with Sasquahanna International Group. Mehdi, your line is now open. Yes, thanks for taking my question. Scott, I want to go back to segmentation of HVM. You highlighted introduction of VHVM, and I want you to double-click on this. Can you help me understand how bandwidth is necessitating the VHP, and how should we think about the tradeoff between bandwidth and density, I think there are some confusion, and in my opinion, bandwidth is priority number one, and perhaps VHDM would give you that extra bandwidth, and this is why there's diversification, but I would like to hear how you see it, especially as it relates to the underlying technology. Thank you. Sure. Thanks, Benny. So the key piece with the HPM is bandwidth, as you point out. That is the enabler. If you think about the kind of bandwidth that can be accomplished and the power levels that can be accomplished by putting the structure directly on top of, you know, an XPU, that is the piece that can't really be done in a different way in terms of that much bandwidth gained. Now, capacity, of course, is more complicated directly on top of GPU because it's a much more difficult thermal management challenge to go to multiple, multiple die stacks. Although you have to go through higher capacities on vertical HPM as well, it doesn't start out as a product that can be built with a large number of die stacks and actually have the power and performance benefit and thermal management. So capacity scales at a different pace there. And the system product ultimately for most systems or for many systems will be, you know, HBM 5, 5E in combination with vertical HBM to get the bandwidth and the system will be optimized around both those things. So, you now, capacity optimization is key and we're working hard to get the capacity up on vertical HPM. But these things, you know, there's also the interplay of these things with trade ratio. So when you look at vertical HBM, it again has a very high trade ratio, both because of the stacking, but also because of the optimization for bandwidth inherently makes the number of IOs much larger, which inherently reduces the diaper wafer on the DRAM. So it's another balance point to all this. But the system vertical HBM ultimately is going to be a huge benefit to our customers as it comes in and provides primarily the bandwidth boost that you mentioned. There are no further questions at this time. I will now turn the call back to Scott DeBoer, President, Chief Technology and Products Officer for closing remarks. Okay, thank you for the opportunity to talk with you all today and good questions. Just wanted to reemphasize that we believe Micron is at its strongest position in history at this point in time. The technology underpinning our products is a key strength of Micron's and we're very focused on the execution it takes to continue that technology leadership. Our products built on that core technology are enabled in a very strong way with our customer collaboration, and we're set up to win in that space due to the depth of partnerships that we're building and have established. And ultimately, in order to manage this complexity and the large number of of customer demands, we are leading the way with AI implementation from basic physics through design and high volume manufacturing and really leveraging that AI to make sure that our execution is stronger than ever. So thank you very much for your time today. This concludes today's call. Thank you for attending. You may now disconnect. Thank you.