Technology and Product Webinar - MICRON TECHNOLOGY INC

Explicit Guidance:

• DRAM Node Ramp Timelines:
  • One Gamma Node: Already in high-volume manufacturing; serving as the primary node for key products ramping over the next 12 months.
  • One Delta Node: Targeted for volume ramp in the second half of 2027; positioned as the fifth consecutive industry leadership node.
  • HBM4E: Expected to follow HBM4 in the roadmap timeline (specific volume dates not disclosed, implied as post-HBM4 ramp).
• NAND Node Ramp Timelines:
  • Gen 11 NAND: Targeted for ramp in the second half of 2027; represents a significant generational leap from Gen 9.
  • Capacity Expectations: Gen 11 will feature >400 layers and >40% higher bit density compared to Gen 9.
• Product Performance Targets:
  • LP6 DRAM: Anticipated to deliver 35% improved power efficiency over LP5 across various densities.
  • DDR6: Targeted to deliver 2x bandwidth compared to DDR5.
  • One Delta Node: Aiming for mid-20s percentage bit density improvement vs. previous node.
  • Gen 11 NAND: Targeting 1.5x faster I/O speeds and reduced data transfer energy vs. Gen 9.

Business-Segment Outlook:

• Data Center Memory:
  • HBM Evolution: Transitioning from standard HBM4/HBM4E to Custom HBM (co-designed with customers) and Vertical HBM (memory stacked directly on processing units) to address bandwidth bottlenecks. Vertical HBM is described as a "key element" for ultimate system performance.
  • DDR/LPDRAM: Continued demand for high-capacity DDR modules and low-power DRAM in data centers; LP6 and DDR6 will be optimized for AI workloads.
  • 512GB DDR5 RDM: Already sampled; next generation expected to deliver 1TB RDM (industry's highest capacity).
• Data Center Storage (NAND):
  • AI-Class NAND: Focus on two distinct architectures: High IOPS AI-class NAND (SLC-based for ultra-fast storage) and High-Bandwidth AI-class NAND (using TSV stack with logic for proximity to accelerators).
  • Capacity Focus: High-capacity SSDs will remain a key focus leveraged by Gen 11 NAND and cost-per-bit improvements.
• Edge & Mobile:
  • Vertical Edge Inference Memory (EIM): New product category optimizing for power efficiency and bandwidth for autonomous vehicles and robotics; distinct from Vertical HBM (lower bandwidth, higher power sensitivity).
  • AI PCs/Mobile: LP6 will be a major focus for mobile; SO-CAM2 modules leveraging LP-D-RAM remain key drivers.
• Supply Chain & Manufacturing:
  • Hybrid Bonding: Identified as a major focus and necessary technology for achieving required interconnect density and bandwidth for HBM and Vertical HBM products.
  • Stacking: Roadmap includes moving to 16-high HBM stacks using hybrid bonding for thermal and bandwidth benefits.

Market and Competitive Outlook:

• Demand Trends:
  • Shortage Outlook: Management expects memory to remain in short supply for the next two years, with no expectation of balance in that period.
  • AI Drivers: Inference and "Agentic AI" phases are driving continuous increases in memory demand, content (bits), and bandwidth requirements.
  • Workload Specificity: While some "despecking" may occur, the core thesis is that memory content will increase to maximize system performance; more memory bandwidth and content correlate directly with better system operation.
• Competitive Positioning:
  • Technology Leadership: Micron claims leadership in DRAM (4 consecutive nodes), HBM (3 generations), and NAND (3 consecutive nodes).
  • Roadmap Uniqueness: Management describes the current position as having the "farthest extended roadmap" in history, with confidence in scaling pathing.
  • 4F Squared Technology: Micron explicitly states that 4F squared is not a viable scaling path beyond current nodes due to physics constraints; intends to transition to 3D DRAM instead. Competitors' moves on 4F squared are characterized as potentially "smoke and mirrors" regarding density gains which are actually driven by capacitor pitch.
  • Foundry Strategy: Base dies for custom HBM and Vertical HBM will utilize advanced foundry nodes (specifics not named) for HBM4E and beyond to optimize power and performance.

Macro / Industry Outlook:

• AI Infrastructure: The "next era of AI" will be defined by the convergence of memory, storage, and compute; memory is identified as the fundamental "limiter" on system performance.
• Token Efficiency: A primary industry focus; memory architecture directly impacts cost per token in AI inference.
• Supply Chain Complexity: Acknowledges increasing "trade ratios" (wafers required per unit of product) for HBM and Vertical HBM relative to standard DRAM, creating capacity pressure.

Strategic Initiatives:

• R&D & Capital Investment:
  • Micron Research Labs: $10 billion commitment over 10 years for long-term research beyond current product roadmaps.
  • Albany Nanotech: Increased capital commitment to advance EUV lithography for the next 5-10 years.
  • Micron Ventures: Ramp-up of investment activity to strengthen ecosystem engagement.
• AI Integration in Execution:
  • R&D Speed: AI tools are accelerating controller design by 2x (50% less time from silicon to tape-out) and SSD product development by >60%.
  • Smart Manufacturing: Leveraging AI for root cause analysis and process optimization across the ecosystem to ramp faster than previous iterations.
• Co-Innovation:
  • Customer Partnerships: Deepening co-design efforts with hyperscalers (e.g., Meta, Weka) for LPDDR6, custom HBM, and Vertical HBM; moving from transactional to "co-imagining, co-designing, co-developing, co-validating."
  • Supply Chain Partnerships: Deepening ties with suppliers for lithography, hybrid bonding, and film processing to enable next-gen capabilities.
• Capacity Expansion:
  • Boise Facility: Center of focus for One Delta node; part of a broader U.S. manufacturing strategy.

Risks and Headwinds to Outlook:

• Physical Scaling Limits: DRAM planar scaling is nearing atomic limits; requires successful transition to 3D DRAM (timing dependent on cost/complexity).
• Thermal Management: Vertical HBM and high-density stacking present significant thermal challenges; requires "thermally aware" co-design with customers.
• Manufacturing Complexity: Hybrid bonding and advanced packaging require high-volume maturity; timing depends on business decisions regarding cost and complexity.
• Trade Ratios: High wafer consumption per unit for HBM/Vertical HBM could strain supply relative to demand if capacity expansion doesn't match the intensity of the shift.
• Execution Risk: Meeting the "insatiable demand" requires flawless execution of new technologies (Gen 11, One Delta, 3D DRAM) and scaling of complex packaging.

Management Tone on the Future:

• Confidence Level: Very High. Describes the current moment as an "unprecedented position" with the "strongest opportunity" and "farthest extended roadmap" of their career.
• Strategic Focus: Shift from reactive scaling to proactive, AI-driven innovation and deep customer co-creation.
• Differentiation: Strong belief that technology leadership (35% power improvements, 2x bandwidth, 400+ layer NAND) and execution speed (AI-accelerated R&D) are key differentiators.
• Hedges: While confident in roadmaps, management notes that 3D DRAM implementation timing is a business decision based on cost/complexity, and custom HBM/base die nodes are customer-dependent decisions.

Miscellaneous:

• HBM4 Capability: One stack delivers 2.8 TB/s bandwidth; ~100 stacks can match total worldwide internet bandwidth (~282 TB/s).
• Innovation Benchmark: Micron cites DRAM industry pace (400x bits on wafer since 1995) far outpacing other industries like automotive.
• Future Nodes: Pathfinding on OneZeta (Angstrom), Ada Angstrom, and 3D DRAM (positioned between OneZeta and One Ada) is underway.